PT2 リリース番号: 01
--------------------------------------------------------------------------------
Release 10.1.03 Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
E:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise E:/RTL/Project/PT2/PT2.ise
-intstyle ise -v 3 -s 4 -xml PT2 PT2.ncd -o PT2.twr PT2.pcf -ucf
E:/RTL/Code/PT2/UCF/PT2.ucf
Design file: PT2.ncd
Physical constraint file: PT2.pcf
Device,package,speed: xc3s200a,ft256,-4 (PRODUCTION 1.41 2008-07-25)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%;
21513 paths analyzed, 3343 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 13.902ns.
--------------------------------------------------------------------------------
Slack: 7.154ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/write/out_gray_1 (FF)
Destination: fifo/fifo/count/write_address_gray_0_1 (FF)
Requirement: 10.000ns
Data Path Delay: 3.944ns (Levels of Logic = 0)
Clock Path Skew: 1.098ns (1.297 - 0.199)
Source Clock: clock_ram rising at 20.000ns
Destination Clock: clock_pci rising at 30.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/write/out_gray_1 to fifo/fifo/count/write_address_gray_0_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y24.XQ Tcko 0.591 fifo/fifo/write/out_gray<1>
fifo/fifo/write/out_gray_1
SLICE_X14Y24.BX net (fanout=1) 3.010 fifo/fifo/write/out_gray<1>
SLICE_X14Y24.CLK Tdick 0.343 fifo/fifo/count/write_address_gray_0_1
fifo/fifo/count/write_address_gray_0_1
------------------------------------------------- ---------------------------
Total 3.944ns (0.934ns logic, 3.010ns route)
(23.7% logic, 76.3% route)
--------------------------------------------------------------------------------
Slack: 7.251ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/write/out_gray_2 (FF)
Destination: fifo/fifo/count/write_address_gray_0_2 (FF)
Requirement: 10.000ns
Data Path Delay: 3.905ns (Levels of Logic = 0)
Clock Path Skew: 1.156ns (1.323 - 0.167)
Source Clock: clock_ram rising at 20.000ns
Destination Clock: clock_pci rising at 30.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/write/out_gray_2 to fifo/fifo/count/write_address_gray_0_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X26Y32.YQ Tcko 0.676 fifo/fifo/write/out_gray<3>
fifo/fifo/write/out_gray_2
SLICE_X26Y33.BY net (fanout=1) 2.843 fifo/fifo/write/out_gray<2>
SLICE_X26Y33.CLK Tdick 0.386 fifo/fifo/count/write_address_gray_0_3
fifo/fifo/count/write_address_gray_0_2
------------------------------------------------- ---------------------------
Total 3.905ns (1.062ns logic, 2.843ns route)
(27.2% logic, 72.8% route)
--------------------------------------------------------------------------------
Slack: 7.310ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/write/out_gray_0 (FF)
Destination: fifo/fifo/count/write_address_gray_0_0 (FF)
Requirement: 10.000ns
Data Path Delay: 3.788ns (Levels of Logic = 0)
Clock Path Skew: 1.098ns (1.297 - 0.199)
Source Clock: clock_ram rising at 20.000ns
Destination Clock: clock_pci rising at 30.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/write/out_gray_0 to fifo/fifo/count/write_address_gray_0_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y24.YQ Tcko 0.580 fifo/fifo/write/out_gray<1>
fifo/fifo/write/out_gray_0
SLICE_X14Y24.BY net (fanout=1) 2.822 fifo/fifo/write/out_gray<0>
SLICE_X14Y24.CLK Tdick 0.386 fifo/fifo/count/write_address_gray_0_1
fifo/fifo/count/write_address_gray_0_0
------------------------------------------------- ---------------------------
Total 3.788ns (0.966ns logic, 2.822ns route)
(25.5% logic, 74.5% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_ts_clock_0 = PERIOD TIMEGRP "ts_clock_0" 16.4 ns HIGH
50%;
1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.433ns.
--------------------------------------------------------------------------------
Slack: 9.967ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[0].packet/a_count_l (FF)
Destination: ts/packet[0].packet/out_data_17 (FF)
Requirement: 16.400ns
Data Path Delay: 6.327ns (Levels of Logic = 3)
Clock Path Skew: -0.106ns (0.540 - 0.646)
Source Clock: clock_ts<0> rising at 0.000ns
Destination Clock: clock_ts<0> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[0].packet/a_count_l to ts/packet[0].packet/out_data_17
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y36.YQ Tcko 0.580 ts/packet[0].packet/b_count_l
ts/packet[0].packet/a_count_l
SLICE_X12Y20.G2 net (fanout=7) 1.603 ts/packet[0].packet/a_count_l
SLICE_X12Y20.Y Tilo 0.707 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>11
SLICE_X12Y20.F4 net (fanout=3) 0.136 ts/packet[0].packet/N1
SLICE_X12Y20.X Tilo 0.692 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>21
SLICE_X7Y16.F2 net (fanout=19) 1.887 ts/packet[0].packet/N9
SLICE_X7Y16.CLK Tfck 0.722 ts/packet[0].packet/out_data<17>
ts/packet[0].packet/out_data_mux0000<14>1
ts/packet[0].packet/out_data_17
------------------------------------------------- ---------------------------
Total 6.327ns (2.701ns logic, 3.626ns route)
(42.7% logic, 57.3% route)
--------------------------------------------------------------------------------
Slack: 9.967ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[0].packet/a_count_l (FF)
Destination: ts/packet[0].packet/out_data_15 (FF)
Requirement: 16.400ns
Data Path Delay: 6.327ns (Levels of Logic = 3)
Clock Path Skew: -0.106ns (0.540 - 0.646)
Source Clock: clock_ts<0> rising at 0.000ns
Destination Clock: clock_ts<0> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[0].packet/a_count_l to ts/packet[0].packet/out_data_15
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y36.YQ Tcko 0.580 ts/packet[0].packet/b_count_l
ts/packet[0].packet/a_count_l
SLICE_X12Y20.G2 net (fanout=7) 1.603 ts/packet[0].packet/a_count_l
SLICE_X12Y20.Y Tilo 0.707 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>11
SLICE_X12Y20.F4 net (fanout=3) 0.136 ts/packet[0].packet/N1
SLICE_X12Y20.X Tilo 0.692 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>21
SLICE_X6Y17.F3 net (fanout=19) 1.807 ts/packet[0].packet/N9
SLICE_X6Y17.CLK Tfck 0.802 ts/packet[0].packet/out_data<15>
ts/packet[0].packet/out_data_mux0000<16>1
ts/packet[0].packet/out_data_15
------------------------------------------------- ---------------------------
Total 6.327ns (2.781ns logic, 3.546ns route)
(44.0% logic, 56.0% route)
--------------------------------------------------------------------------------
Slack: 9.997ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[0].packet/a_count_h (FF)
Destination: ts/packet[0].packet/out_data_17 (FF)
Requirement: 16.400ns
Data Path Delay: 6.260ns (Levels of Logic = 3)
Clock Path Skew: -0.143ns (0.540 - 0.683)
Source Clock: clock_ts<0> rising at 0.000ns
Destination Clock: clock_ts<0> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[0].packet/a_count_h to ts/packet[0].packet/out_data_17
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X17Y28.XQ Tcko 0.591 ts/packet[0].packet/a_count_h
ts/packet[0].packet/a_count_h
SLICE_X12Y20.G4 net (fanout=7) 1.525 ts/packet[0].packet/a_count_h
SLICE_X12Y20.Y Tilo 0.707 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>11
SLICE_X12Y20.F4 net (fanout=3) 0.136 ts/packet[0].packet/N1
SLICE_X12Y20.X Tilo 0.692 ts/packet[0].packet/N9
ts/packet[0].packet/out_data_mux0000<10>21
SLICE_X7Y16.F2 net (fanout=19) 1.887 ts/packet[0].packet/N9
SLICE_X7Y16.CLK Tfck 0.722 ts/packet[0].packet/out_data<17>
ts/packet[0].packet/out_data_mux0000<14>1
ts/packet[0].packet/out_data_17
------------------------------------------------- ---------------------------
Total 6.260ns (2.712ns logic, 3.548ns route)
(43.3% logic, 56.7% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_ts_clock_1 = PERIOD TIMEGRP "ts_clock_1" 26.2 ns HIGH
50%;
1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.700ns.
--------------------------------------------------------------------------------
Slack: 19.500ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/io[1].io/out_ts_enable (FF)
Destination: ts/packet[1].packet/count_h_1 (FF)
Requirement: 26.200ns
Data Path Delay: 6.588ns (Levels of Logic = 2)
Clock Path Skew: -0.112ns (0.565 - 0.677)
Source Clock: clock_ts<1> rising at 0.000ns
Destination Clock: clock_ts<1> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/io[1].io/out_ts_enable to ts/packet[1].packet/count_h_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X12Y30.YQ Tcko 0.676 ts/io[1].io/out_ts_enable
ts/io[1].io/out_ts_enable
SLICE_X21Y36.G3 net (fanout=4) 2.144 ts/io[1].io/out_ts_enable
SLICE_X21Y36.Y Tilo 0.648 ts/packet[1].packet/count_h_not0001
ts/packet[1].packet/count_h_not00015
SLICE_X21Y36.F1 net (fanout=1) 0.704 ts/packet[1].packet/count_h_not00015
SLICE_X21Y36.X Tilo 0.643 ts/packet[1].packet/count_h_not0001
ts/packet[1].packet/count_h_not000139
SLICE_X20Y36.CE net (fanout=5) 1.462 ts/packet[1].packet/count_h_not0001
SLICE_X20Y36.CLK Tceck 0.311 ts/packet[1].packet/count_h<1>
ts/packet[1].packet/count_h_1
------------------------------------------------- ---------------------------
Total 6.588ns (2.278ns logic, 4.310ns route)
(34.6% logic, 65.4% route)
--------------------------------------------------------------------------------
Slack: 19.711ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/io[1].io/out_ts_enable (FF)
Destination: ts/packet[1].packet/count_h_0 (FF)
Requirement: 26.200ns
Data Path Delay: 6.377ns (Levels of Logic = 2)
Clock Path Skew: -0.112ns (0.565 - 0.677)
Source Clock: clock_ts<1> rising at 0.000ns
Destination Clock: clock_ts<1> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/io[1].io/out_ts_enable to ts/packet[1].packet/count_h_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X12Y30.YQ Tcko 0.676 ts/io[1].io/out_ts_enable
ts/io[1].io/out_ts_enable
SLICE_X21Y36.G3 net (fanout=4) 2.144 ts/io[1].io/out_ts_enable
SLICE_X21Y36.Y Tilo 0.648 ts/packet[1].packet/count_h_not0001
ts/packet[1].packet/count_h_not00015
SLICE_X21Y36.F1 net (fanout=1) 0.704 ts/packet[1].packet/count_h_not00015
SLICE_X21Y36.X Tilo 0.643 ts/packet[1].packet/count_h_not0001
ts/packet[1].packet/count_h_not000139
SLICE_X21Y37.CE net (fanout=5) 1.251 ts/packet[1].packet/count_h_not0001
SLICE_X21Y37.CLK Tceck 0.311 ts/packet[1].packet/count_h<0>
ts/packet[1].packet/count_h_0
------------------------------------------------- ---------------------------
Total 6.377ns (2.278ns logic, 4.099ns route)
(35.7% logic, 64.3% route)
--------------------------------------------------------------------------------
Slack: 19.784ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[1].packet/a_count_h (FF)
Destination: ts/packet[1].packet/count_2 (FF)
Requirement: 26.200ns
Data Path Delay: 6.306ns (Levels of Logic = 3)
Clock Path Skew: -0.110ns (0.557 - 0.667)
Source Clock: clock_ts<1> rising at 0.000ns
Destination Clock: clock_ts<1> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[1].packet/a_count_h to ts/packet[1].packet/count_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y35.XQ Tcko 0.591 ts/packet[1].packet/a_count_h
ts/packet[1].packet/a_count_h
SLICE_X12Y25.G4 net (fanout=7) 1.338 ts/packet[1].packet/a_count_h
SLICE_X12Y25.Y Tilo 0.707 ts/packet[1].packet/N9
ts/packet[1].packet/out_data_mux0000<10>11
SLICE_X12Y24.G3 net (fanout=3) 0.128 ts/packet[1].packet/N1
SLICE_X12Y24.Y Tilo 0.707 ts/packet[1].packet/out_data<24>
ts/packet[1].packet/out_data_mux0000<1>21
SLICE_X8Y22.F3 net (fanout=6) 0.696 ts/packet[1].packet/N14
SLICE_X8Y22.X Tilo 0.692 ts/packet[1].packet/out_data<25>
ts/packet[1].packet/count_not00011
SLICE_X9Y22.CE net (fanout=2) 1.136 ts/packet[1].packet/count_not0001
SLICE_X9Y22.CLK Tceck 0.311 ts/packet[1].packet/count<2>
ts/packet[1].packet/count_2
------------------------------------------------- ---------------------------
Total 6.306ns (3.008ns logic, 3.298ns route)
(47.7% logic, 52.3% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_ts_clock_2 = PERIOD TIMEGRP "ts_clock_2" 16.4 ns HIGH
50%;
1204 paths analyzed, 556 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.601ns.
--------------------------------------------------------------------------------
Slack: 9.799ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[2].packet/a_count_h (FF)
Destination: ts/packet[2].packet/out_data_12 (FF)
Requirement: 16.400ns
Data Path Delay: 6.504ns (Levels of Logic = 3)
Clock Path Skew: -0.097ns (0.558 - 0.655)
Source Clock: clock_ts<2> rising at 0.000ns
Destination Clock: clock_ts<2> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[2].packet/a_count_h to ts/packet[2].packet/out_data_12
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X23Y27.XQ Tcko 0.591 ts/packet[2].packet/a_count_h
ts/packet[2].packet/a_count_h
SLICE_X15Y15.G1 net (fanout=7) 1.785 ts/packet[2].packet/a_count_h
SLICE_X15Y15.Y Tilo 0.648 ts/packet[2].packet/N9
ts/packet[2].packet/out_data_mux0000<10>11
SLICE_X15Y15.F4 net (fanout=3) 0.120 ts/packet[2].packet/N1
SLICE_X15Y15.X Tilo 0.643 ts/packet[2].packet/N9
ts/packet[2].packet/out_data_mux0000<10>21
SLICE_X4Y6.G4 net (fanout=19) 1.900 ts/packet[2].packet/N9
SLICE_X4Y6.CLK Tgck 0.817 ts/packet[2].packet/out_data<13>
ts/packet[2].packet/out_data_mux0000<19>1
ts/packet[2].packet/out_data_12
------------------------------------------------- ---------------------------
Total 6.504ns (2.699ns logic, 3.805ns route)
(41.5% logic, 58.5% route)
--------------------------------------------------------------------------------
Slack: 9.879ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[2].packet/a_count_h (FF)
Destination: ts/packet[2].packet/count_2 (FF)
Requirement: 16.400ns
Data Path Delay: 6.419ns (Levels of Logic = 3)
Clock Path Skew: -0.102ns (0.553 - 0.655)
Source Clock: clock_ts<2> rising at 0.000ns
Destination Clock: clock_ts<2> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[2].packet/a_count_h to ts/packet[2].packet/count_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X23Y27.XQ Tcko 0.591 ts/packet[2].packet/a_count_h
ts/packet[2].packet/a_count_h
SLICE_X15Y15.G1 net (fanout=7) 1.785 ts/packet[2].packet/a_count_h
SLICE_X15Y15.Y Tilo 0.648 ts/packet[2].packet/N9
ts/packet[2].packet/out_data_mux0000<10>11
SLICE_X12Y12.G1 net (fanout=3) 0.547 ts/packet[2].packet/N1
SLICE_X12Y12.Y Tilo 0.707 ts/packet[2].packet/out_data<24>
ts/packet[2].packet/out_data_mux0000<1>21
SLICE_X14Y12.F2 net (fanout=6) 0.483 ts/packet[2].packet/N14
SLICE_X14Y12.X Tilo 0.692 ts/packet[2].packet/out_data<25>
ts/packet[2].packet/count_not00011
SLICE_X13Y12.CE net (fanout=2) 0.655 ts/packet[2].packet/count_not0001
SLICE_X13Y12.CLK Tceck 0.311 ts/packet[2].packet/count<2>
ts/packet[2].packet/count_2
------------------------------------------------- ---------------------------
Total 6.419ns (2.949ns logic, 3.470ns route)
(45.9% logic, 54.1% route)
--------------------------------------------------------------------------------
Slack: 10.056ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[2].packet/count_h_1 (FF)
Destination: ts/packet[2].packet/count_h_2 (FF)
Requirement: 16.400ns
Data Path Delay: 6.301ns (Levels of Logic = 3)
Clock Path Skew: -0.043ns (0.228 - 0.271)
Source Clock: clock_ts<2> rising at 0.000ns
Destination Clock: clock_ts<2> rising at 16.400ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[2].packet/count_h_1 to ts/packet[2].packet/count_h_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X24Y24.XQ Tcko 0.631 ts/packet[2].packet/count_h<1>
ts/packet[2].packet/count_h_1
SLICE_X23Y26.G2 net (fanout=7) 1.250 ts/packet[2].packet/count_h<1>
SLICE_X23Y26.Y Tilo 0.648 ts/packet[2].packet/count_h_not000112
ts/packet[2].packet/count_h_mux0000<1>11
SLICE_X23Y26.F3 net (fanout=3) 0.077 ts/packet[2].packet/N7
SLICE_X23Y26.X Tilo 0.643 ts/packet[2].packet/count_h_not000112
ts/packet[2].packet/count_h_not000112
SLICE_X26Y22.F2 net (fanout=1) 0.910 ts/packet[2].packet/count_h_not000112
SLICE_X26Y22.X Tilo 0.692 ts/packet[2].packet/count_h_not0001
ts/packet[2].packet/count_h_not000139
SLICE_X26Y27.CE net (fanout=5) 1.139 ts/packet[2].packet/count_h_not0001
SLICE_X26Y27.CLK Tceck 0.311 ts/packet[2].packet/count_h<3>
ts/packet[2].packet/count_h_2
------------------------------------------------- ---------------------------
Total 6.301ns (2.925ns logic, 3.376ns route)
(46.4% logic, 53.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_ts_clock_3 = PERIOD TIMEGRP "ts_clock_3" 26.2 ns HIGH
50%;
1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 7.804ns.
--------------------------------------------------------------------------------
Slack: 18.396ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[3].packet/a_count_h (FF)
Destination: ts/packet[3].packet/count_2 (FF)
Requirement: 26.200ns
Data Path Delay: 7.723ns (Levels of Logic = 3)
Clock Path Skew: -0.081ns (0.562 - 0.643)
Source Clock: clock_ts<3> rising at 0.000ns
Destination Clock: clock_ts<3> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[3].packet/a_count_h to ts/packet[3].packet/count_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y13.XQ Tcko 0.631 ts/packet[3].packet/a_count_h
ts/packet[3].packet/a_count_h
SLICE_X6Y6.G4 net (fanout=7) 1.558 ts/packet[3].packet/a_count_h
SLICE_X6Y6.Y Tilo 0.707 ts/packet[3].packet/N9
ts/packet[3].packet/out_data_mux0000<10>11
SLICE_X6Y5.G4 net (fanout=3) 0.473 ts/packet[3].packet/N1
SLICE_X6Y5.Y Tilo 0.707 ts/packet[3].packet/out_data<24>
ts/packet[3].packet/out_data_mux0000<1>21
SLICE_X12Y8.F2 net (fanout=6) 1.415 ts/packet[3].packet/N14
SLICE_X12Y8.X Tilo 0.692 ts/packet[3].packet/out_data<25>
ts/packet[3].packet/count_not00011
SLICE_X13Y8.CE net (fanout=2) 1.229 ts/packet[3].packet/count_not0001
SLICE_X13Y8.CLK Tceck 0.311 ts/packet[3].packet/count<2>
ts/packet[3].packet/count_2
------------------------------------------------- ---------------------------
Total 7.723ns (3.048ns logic, 4.675ns route)
(39.5% logic, 60.5% route)
--------------------------------------------------------------------------------
Slack: 19.259ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[3].packet/a_count_h (FF)
Destination: ts/packet[3].packet/count_0 (FF)
Requirement: 26.200ns
Data Path Delay: 6.860ns (Levels of Logic = 3)
Clock Path Skew: -0.081ns (0.562 - 0.643)
Source Clock: clock_ts<3> rising at 0.000ns
Destination Clock: clock_ts<3> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[3].packet/a_count_h to ts/packet[3].packet/count_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y13.XQ Tcko 0.631 ts/packet[3].packet/a_count_h
ts/packet[3].packet/a_count_h
SLICE_X6Y6.G4 net (fanout=7) 1.558 ts/packet[3].packet/a_count_h
SLICE_X6Y6.Y Tilo 0.707 ts/packet[3].packet/N9
ts/packet[3].packet/out_data_mux0000<10>11
SLICE_X6Y5.G4 net (fanout=3) 0.473 ts/packet[3].packet/N1
SLICE_X6Y5.Y Tilo 0.707 ts/packet[3].packet/out_data<24>
ts/packet[3].packet/out_data_mux0000<1>21
SLICE_X12Y8.F2 net (fanout=6) 1.415 ts/packet[3].packet/N14
SLICE_X12Y8.X Tilo 0.692 ts/packet[3].packet/out_data<25>
ts/packet[3].packet/count_not00011
SLICE_X12Y9.CE net (fanout=2) 0.366 ts/packet[3].packet/count_not0001
SLICE_X12Y9.CLK Tceck 0.311 ts/packet[3].packet/count<0>
ts/packet[3].packet/count_0
------------------------------------------------- ---------------------------
Total 6.860ns (3.048ns logic, 3.812ns route)
(44.4% logic, 55.6% route)
--------------------------------------------------------------------------------
Slack: 19.259ns (requirement - (data path - clock path skew + uncertainty))
Source: ts/packet[3].packet/a_count_h (FF)
Destination: ts/packet[3].packet/count_1 (FF)
Requirement: 26.200ns
Data Path Delay: 6.860ns (Levels of Logic = 3)
Clock Path Skew: -0.081ns (0.562 - 0.643)
Source Clock: clock_ts<3> rising at 0.000ns
Destination Clock: clock_ts<3> rising at 26.200ns
Clock Uncertainty: 0.000ns
Maximum Data Path: ts/packet[3].packet/a_count_h to ts/packet[3].packet/count_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y13.XQ Tcko 0.631 ts/packet[3].packet/a_count_h
ts/packet[3].packet/a_count_h
SLICE_X6Y6.G4 net (fanout=7) 1.558 ts/packet[3].packet/a_count_h
SLICE_X6Y6.Y Tilo 0.707 ts/packet[3].packet/N9
ts/packet[3].packet/out_data_mux0000<10>11
SLICE_X6Y5.G4 net (fanout=3) 0.473 ts/packet[3].packet/N1
SLICE_X6Y5.Y Tilo 0.707 ts/packet[3].packet/out_data<24>
ts/packet[3].packet/out_data_mux0000<1>21
SLICE_X12Y8.F2 net (fanout=6) 1.415 ts/packet[3].packet/N14
SLICE_X12Y8.X Tilo 0.692 ts/packet[3].packet/out_data<25>
ts/packet[3].packet/count_not00011
SLICE_X12Y9.CE net (fanout=2) 0.366 ts/packet[3].packet/count_not0001
SLICE_X12Y9.CLK Tceck 0.311 ts/packet[3].packet/count<0>
ts/packet[3].packet/count_1
------------------------------------------------- ---------------------------
Total 6.860ns (3.048ns logic, 3.812ns route)
(44.4% logic, 55.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP
"clock_pci_ram_clock" TS_pci_clock / 3 HIGH 50%;
6551 paths analyzed, 1022 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 9.286ns.
--------------------------------------------------------------------------------
Slack: 0.714ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/count/out_write_count_8 (FF)
Destination: ram/ram/read_address_3 (FF)
Requirement: 10.000ns
Data Path Delay: 9.230ns (Levels of Logic = 4)
Clock Path Skew: -0.056ns (0.613 - 0.669)
Source Clock: clock_ram rising at 0.000ns
Destination Clock: clock_ram rising at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/count/out_write_count_8 to ram/ram/read_address_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X19Y32.XQ Tcko 0.591 fifo/fifo/count/out_write_count<8>
fifo/fifo/count/out_write_count_8
SLICE_X17Y30.G1 net (fanout=1) 0.817 fifo/fifo/count/out_write_count<8>
SLICE_X17Y30.COUT Topcyg 1.178 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
ram/ram/Mcompar_read_begin_cmp_le0000_lut<3>
ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.CIN net (fanout=1) 0.000 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.XB Tcinxb 0.296 ram/ram/read_begin_cmp_le0000
ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
SLICE_X10Y26.F2 net (fanout=1) 1.227 ram/ram/read_begin_cmp_le0000
SLICE_X10Y26.X Tilo 0.692 ram/ram/read_begin
ram/ram/read_begin43
SLICE_X27Y26.G3 net (fanout=8) 1.342 ram/ram/read_begin
SLICE_X27Y26.Y Tilo 0.648 ram/ram/page_address_not0001
ram/ram/page_count_not000111
SLICE_X31Y20.CE net (fanout=8) 2.128 ram/ram/read_address_not0001
SLICE_X31Y20.CLK Tceck 0.311 ram/ram/read_address<2>
ram/ram/read_address_3
------------------------------------------------- ---------------------------
Total 9.230ns (3.716ns logic, 5.514ns route)
(40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
Slack: 0.714ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/count/out_write_count_8 (FF)
Destination: ram/ram/read_address_5 (FF)
Requirement: 10.000ns
Data Path Delay: 9.230ns (Levels of Logic = 4)
Clock Path Skew: -0.056ns (0.613 - 0.669)
Source Clock: clock_ram rising at 0.000ns
Destination Clock: clock_ram rising at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/count/out_write_count_8 to ram/ram/read_address_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X19Y32.XQ Tcko 0.591 fifo/fifo/count/out_write_count<8>
fifo/fifo/count/out_write_count_8
SLICE_X17Y30.G1 net (fanout=1) 0.817 fifo/fifo/count/out_write_count<8>
SLICE_X17Y30.COUT Topcyg 1.178 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
ram/ram/Mcompar_read_begin_cmp_le0000_lut<3>
ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.CIN net (fanout=1) 0.000 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.XB Tcinxb 0.296 ram/ram/read_begin_cmp_le0000
ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
SLICE_X10Y26.F2 net (fanout=1) 1.227 ram/ram/read_begin_cmp_le0000
SLICE_X10Y26.X Tilo 0.692 ram/ram/read_begin
ram/ram/read_begin43
SLICE_X27Y26.G3 net (fanout=8) 1.342 ram/ram/read_begin
SLICE_X27Y26.Y Tilo 0.648 ram/ram/page_address_not0001
ram/ram/page_count_not000111
SLICE_X31Y21.CE net (fanout=8) 2.128 ram/ram/read_address_not0001
SLICE_X31Y21.CLK Tceck 0.311 ram/ram/read_address<4>
ram/ram/read_address_5
------------------------------------------------- ---------------------------
Total 9.230ns (3.716ns logic, 5.514ns route)
(40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
Slack: 0.714ns (requirement - (data path - clock path skew + uncertainty))
Source: fifo/fifo/count/out_write_count_8 (FF)
Destination: ram/ram/read_address_4 (FF)
Requirement: 10.000ns
Data Path Delay: 9.230ns (Levels of Logic = 4)
Clock Path Skew: -0.056ns (0.613 - 0.669)
Source Clock: clock_ram rising at 0.000ns
Destination Clock: clock_ram rising at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: fifo/fifo/count/out_write_count_8 to ram/ram/read_address_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X19Y32.XQ Tcko 0.591 fifo/fifo/count/out_write_count<8>
fifo/fifo/count/out_write_count_8
SLICE_X17Y30.G1 net (fanout=1) 0.817 fifo/fifo/count/out_write_count<8>
SLICE_X17Y30.COUT Topcyg 1.178 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
ram/ram/Mcompar_read_begin_cmp_le0000_lut<3>
ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.CIN net (fanout=1) 0.000 ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
SLICE_X17Y31.XB Tcinxb 0.296 ram/ram/read_begin_cmp_le0000
ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
SLICE_X10Y26.F2 net (fanout=1) 1.227 ram/ram/read_begin_cmp_le0000
SLICE_X10Y26.X Tilo 0.692 ram/ram/read_begin
ram/ram/read_begin43
SLICE_X27Y26.G3 net (fanout=8) 1.342 ram/ram/read_begin
SLICE_X27Y26.Y Tilo 0.648 ram/ram/page_address_not0001
ram/ram/page_count_not000111
SLICE_X31Y21.CE net (fanout=8) 2.128 ram/ram/read_address_not0001
SLICE_X31Y21.CLK Tceck 0.311 ram/ram/read_address<4>
ram/ram/read_address_4
------------------------------------------------- ---------------------------
Total 9.230ns (3.716ns logic, 5.514ns route)
(40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP
"in_pci_clock";
1076 paths analyzed, 255 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 5.981ns.
--------------------------------------------------------------------------------
Slack: 0.019ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: io_pci_trdy (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_18 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 6.000ns
Data Path Delay: 8.347ns (Levels of Logic = 5)
Clock Path Delay: 2.366ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G3.I Tiopi 1.256 io_pci_trdy
io_pci_trdy
io_pci_trdy_IOBUF/IBUF
io_pci_trdy.DELAY_ADJ
ProtoComp114.ISELMUX.3
SLICE_X2Y39.F2 net (fanout=21) 0.701 N2111
SLICE_X2Y39.X Tilo 0.692 N506
pci/pci/initiator/ad/out_pci_a_enable13_SW0_G
SLICE_X4Y37.G3 net (fanout=1) 0.706 N506
SLICE_X4Y37.X Tif5x 0.987 pci/pci/initiator/ad/out_pci_a_enable41
pci/pci/initiator/ad/out_pci_a_enable41_F
pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.G3 net (fanout=4) 0.724 pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.Y Tilo 0.648 pci/pci/ad_cbe/out_pci_ad<31>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145_1
SLICE_X12Y46.F1 net (fanout=16) 1.831 pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145
SLICE_X12Y46.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<18>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux000010132
pci/pci/ad_cbe/out_pci_ad_18
------------------------------------------------- ---------------------------
Total 8.347ns (4.385ns logic, 3.962ns route)
(52.5% logic, 47.5% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X12Y46.CLK net (fanout=723) 0.844 clock_pci
------------------------------------------------- ---------------------------
Total 2.366ns (1.285ns logic, 1.081ns route)
(54.3% logic, 45.7% route)
--------------------------------------------------------------------------------
Slack: 0.039ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: io_pci_trdy (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_25 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 6.000ns
Data Path Delay: 8.353ns (Levels of Logic = 6)
Clock Path Delay: 2.392ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_25
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G3.I Tiopi 1.256 io_pci_trdy
io_pci_trdy
io_pci_trdy_IOBUF/IBUF
io_pci_trdy.DELAY_ADJ
ProtoComp114.ISELMUX.3
SLICE_X4Y40.G1 net (fanout=21) 0.927 N2111
SLICE_X4Y40.Y Tilo 0.707 fifo/_COND_65<1>
pci/pci/initiator/out_local_done_mux0000112
SLICE_X4Y40.F4 net (fanout=21) 0.182 pci/pci/initiator/N12
SLICE_X4Y40.X Tilo 0.692 fifo/_COND_65<1>
fifo/_COND_65<1>1
SLICE_X12Y42.F2 net (fanout=32) 1.821 fifo/_COND_65<1>
SLICE_X12Y42.X Tilo 0.692 fifo_read_data<25>
fifo/Mram_read_data26.SLICEM_F
SLICE_X8Y42.F1 net (fanout=1) 0.427 fifo_read_data<25>
SLICE_X8Y42.X Tilo 0.692 pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001872
pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001872
SLICE_X8Y43.F1 net (fanout=1) 0.155 pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001872
SLICE_X8Y43.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<25>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001898
pci/pci/ad_cbe/out_pci_ad_25
------------------------------------------------- ---------------------------
Total 8.353ns (4.841ns logic, 3.512ns route)
(58.0% logic, 42.0% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_25
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X8Y43.CLK net (fanout=723) 0.870 clock_pci
------------------------------------------------- ---------------------------
Total 2.392ns (1.285ns logic, 1.107ns route)
(53.7% logic, 46.3% route)
--------------------------------------------------------------------------------
Slack: 0.066ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: io_pci_stop (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_18 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 6.000ns
Data Path Delay: 8.300ns (Levels of Logic = 5)
Clock Path Delay: 2.366ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: io_pci_stop to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H4.I Tiopi 1.256 io_pci_stop
io_pci_stop
io_pci_stop_IOBUF/IBUF
io_pci_stop.DELAY_ADJ
ProtoComp114.ISELMUX.4
SLICE_X2Y39.F4 net (fanout=15) 0.654 N209
SLICE_X2Y39.X Tilo 0.692 N506
pci/pci/initiator/ad/out_pci_a_enable13_SW0_G
SLICE_X4Y37.G3 net (fanout=1) 0.706 N506
SLICE_X4Y37.X Tif5x 0.987 pci/pci/initiator/ad/out_pci_a_enable41
pci/pci/initiator/ad/out_pci_a_enable41_F
pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.G3 net (fanout=4) 0.724 pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.Y Tilo 0.648 pci/pci/ad_cbe/out_pci_ad<31>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145_1
SLICE_X12Y46.F1 net (fanout=16) 1.831 pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145
SLICE_X12Y46.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<18>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux000010132
pci/pci/ad_cbe/out_pci_ad_18
------------------------------------------------- ---------------------------
Total 8.300ns (4.385ns logic, 3.915ns route)
(52.8% logic, 47.2% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X12Y46.CLK net (fanout=723) 0.844 clock_pci
------------------------------------------------- ---------------------------
Total 2.366ns (1.285ns logic, 1.081ns route)
(54.3% logic, 45.7% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE
COMP "in_pci_clock";
321 paths analyzed, 95 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 8.202ns.
--------------------------------------------------------------------------------
Slack: 0.798ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_pci_gnt (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_18 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.568ns (Levels of Logic = 6)
Clock Path Delay: 2.366ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C7.I Tiopi 1.256 in_pci_gnt
in_pci_gnt
in_pci_gnt_IBUF
in_pci_gnt.DELAY_ADJ
SLICE_X3Y39.G3 net (fanout=8) 1.423 in_pci_gnt_IBUF
SLICE_X3Y39.Y Tilo 0.648 N508
pci/pci/initiator/continue1
SLICE_X3Y39.F1 net (fanout=7) 0.884 pci/pci/initiator/continue
SLICE_X3Y39.X Tilo 0.643 N508
pci/pci/initiator/ad/out_pci_a_enable13_SW1_G
SLICE_X4Y37.F4 net (fanout=1) 0.722 N508
SLICE_X4Y37.X Tif5x 0.987 pci/pci/initiator/ad/out_pci_a_enable41
pci/pci/initiator/ad/out_pci_a_enable41_G
pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.G3 net (fanout=4) 0.724 pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X11Y40.Y Tilo 0.648 pci/pci/ad_cbe/out_pci_ad<31>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145_1
SLICE_X12Y46.F1 net (fanout=16) 1.831 pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145
SLICE_X12Y46.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<18>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux000010132
pci/pci/ad_cbe/out_pci_ad_18
------------------------------------------------- ---------------------------
Total 10.568ns (4.984ns logic, 5.584ns route)
(47.2% logic, 52.8% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_18
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X12Y46.CLK net (fanout=723) 0.844 clock_pci
------------------------------------------------- ---------------------------
Total 2.366ns (1.285ns logic, 1.081ns route)
(54.3% logic, 45.7% route)
--------------------------------------------------------------------------------
Slack: 1.127ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_pci_gnt (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_9 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.308ns (Levels of Logic = 6)
Clock Path Delay: 2.435ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C7.I Tiopi 1.256 in_pci_gnt
in_pci_gnt
in_pci_gnt_IBUF
in_pci_gnt.DELAY_ADJ
SLICE_X3Y39.G3 net (fanout=8) 1.423 in_pci_gnt_IBUF
SLICE_X3Y39.Y Tilo 0.648 N508
pci/pci/initiator/continue1
SLICE_X3Y39.F1 net (fanout=7) 0.884 pci/pci/initiator/continue
SLICE_X3Y39.X Tilo 0.643 N508
pci/pci/initiator/ad/out_pci_a_enable13_SW1_G
SLICE_X4Y37.F4 net (fanout=1) 0.722 N508
SLICE_X4Y37.X Tif5x 0.987 pci/pci/initiator/ad/out_pci_a_enable41
pci/pci/initiator/ad/out_pci_a_enable41_G
pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X8Y43.G4 net (fanout=4) 0.761 pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X8Y43.Y Tilo 0.707 pci/pci/ad_cbe/out_pci_ad<25>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145
SLICE_X12Y36.F2 net (fanout=16) 1.475 pci/pci/ad_cbe/Mmux_out_pci_ad_mux000010115
SLICE_X12Y36.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<9>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux000032155
pci/pci/ad_cbe/out_pci_ad_9
------------------------------------------------- ---------------------------
Total 10.308ns (5.043ns logic, 5.265ns route)
(48.9% logic, 51.1% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X12Y36.CLK net (fanout=723) 0.913 clock_pci
------------------------------------------------- ---------------------------
Total 2.435ns (1.285ns logic, 1.150ns route)
(52.8% logic, 47.2% route)
--------------------------------------------------------------------------------
Slack: 1.188ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_pci_gnt (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_13 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.289ns (Levels of Logic = 6)
Clock Path Delay: 2.477ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C7.I Tiopi 1.256 in_pci_gnt
in_pci_gnt
in_pci_gnt_IBUF
in_pci_gnt.DELAY_ADJ
SLICE_X3Y39.G3 net (fanout=8) 1.423 in_pci_gnt_IBUF
SLICE_X3Y39.Y Tilo 0.648 N508
pci/pci/initiator/continue1
SLICE_X3Y39.F1 net (fanout=7) 0.884 pci/pci/initiator/continue
SLICE_X3Y39.X Tilo 0.643 N508
pci/pci/initiator/ad/out_pci_a_enable13_SW1_G
SLICE_X4Y37.F4 net (fanout=1) 0.722 N508
SLICE_X4Y37.X Tif5x 0.987 pci/pci/initiator/ad/out_pci_a_enable41
pci/pci/initiator/ad/out_pci_a_enable41_G
pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X8Y43.G4 net (fanout=4) 0.761 pci/pci/initiator/ad/out_pci_a_enable41
SLICE_X8Y43.Y Tilo 0.707 pci/pci/ad_cbe/out_pci_ad<25>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000145
SLICE_X10Y33.F4 net (fanout=16) 1.456 pci/pci/ad_cbe/Mmux_out_pci_ad_mux000010115
SLICE_X10Y33.CLK Tfck 0.802 pci/pci/ad_cbe/out_pci_ad<13>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux00005139
pci/pci/ad_cbe/out_pci_ad_13
------------------------------------------------- ---------------------------
Total 10.289ns (5.043ns logic, 5.246ns route)
(49.0% logic, 51.0% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.086 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.237 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.199 clock_pci_BUFG
clock_pci_BUFG
SLICE_X10Y33.CLK net (fanout=723) 0.955 clock_pci
------------------------------------------------- ---------------------------
Total 2.477ns (1.285ns logic, 1.192ns route)
(51.9% logic, 48.1% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP
"in_pci_clock";
84 paths analyzed, 42 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
Minimum allowable offset is 9.856ns.
--------------------------------------------------------------------------------
Slack: 0.144ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pci/pci/ad_cbe/out_pci_ad_enable (FF)
Destination: io_pci_ad<11> (PAD)
Source Clock: clock_pci rising at 0.000ns
Requirement: 10.000ns
Data Path Delay: 7.052ns (Levels of Logic = 1)
Clock Path Delay: 2.804ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.256 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.296 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.221 clock_pci_BUFG
clock_pci_BUFG
SLICE_X5Y40.CLK net (fanout=723) 1.031 clock_pci
------------------------------------------------- ---------------------------
Total 2.804ns (1.477ns logic, 1.327ns route)
(52.7% logic, 47.3% route)
Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<11>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X5Y40.XQ Tcko 0.591 pci/pci/ad_cbe/out_pci_ad_enable
pci/pci/ad_cbe/out_pci_ad_enable
K3.T1 net (fanout=33) 3.445 pci/pci/ad_cbe/out_pci_ad_enable
K3.PAD Tiotp 3.016 io_pci_ad<11>
io_pci_ad_11_IOBUF/OBUFT
io_pci_ad<11>
------------------------------------------------- ---------------------------
Total 7.052ns (3.607ns logic, 3.445ns route)
(51.1% logic, 48.9% route)
--------------------------------------------------------------------------------
Slack: 0.413ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pci/pci/ad_cbe/out_pci_ad_enable (FF)
Destination: io_pci_ad<14> (PAD)
Source Clock: clock_pci rising at 0.000ns
Requirement: 10.000ns
Data Path Delay: 6.783ns (Levels of Logic = 1)
Clock Path Delay: 2.804ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.256 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.296 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.221 clock_pci_BUFG
clock_pci_BUFG
SLICE_X5Y40.CLK net (fanout=723) 1.031 clock_pci
------------------------------------------------- ---------------------------
Total 2.804ns (1.477ns logic, 1.327ns route)
(52.7% logic, 47.3% route)
Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<14>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X5Y40.XQ Tcko 0.591 pci/pci/ad_cbe/out_pci_ad_enable
pci/pci/ad_cbe/out_pci_ad_enable
L1.T1 net (fanout=33) 3.176 pci/pci/ad_cbe/out_pci_ad_enable
L1.PAD Tiotp 3.016 io_pci_ad<14>
io_pci_ad_14_IOBUF/OBUFT
io_pci_ad<14>
------------------------------------------------- ---------------------------
Total 6.783ns (3.607ns logic, 3.176ns route)
(53.2% logic, 46.8% route)
--------------------------------------------------------------------------------
Slack: 0.525ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pci/pci/ad_cbe/out_pci_ad_2 (FF)
Destination: io_pci_ad<2> (PAD)
Source Clock: clock_pci rising at 0.000ns
Requirement: 10.000ns
Data Path Delay: 6.655ns (Levels of Logic = 1)
Clock Path Delay: 2.820ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.256 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.296 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.221 clock_pci_BUFG
clock_pci_BUFG
SLICE_X9Y41.CLK net (fanout=723) 1.047 clock_pci
------------------------------------------------- ---------------------------
Total 2.820ns (1.477ns logic, 1.343ns route)
(52.4% logic, 47.6% route)
Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_2 to io_pci_ad<2>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y41.XQ Tcko 0.591 pci/pci/ad_cbe/out_pci_ad<2>
pci/pci/ad_cbe/out_pci_ad_2
M4.O1 net (fanout=2) 2.823 pci/pci/ad_cbe/out_pci_ad<2>
M4.PAD Tioop 3.241 io_pci_ad<2>
io_pci_ad_2_IOBUF/OBUFT
io_pci_ad<2>
------------------------------------------------- ---------------------------
Total 6.655ns (3.832ns logic, 2.823ns route)
(57.6% logic, 42.4% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP
"in_pci_clock";
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected.
Minimum allowable offset is 8.089ns.
--------------------------------------------------------------------------------
Slack: 2.911ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pci/pci/initiator/enable (FF)
Destination: out_pci_req (PAD)
Source Clock: clock_pci rising at 0.000ns
Requirement: 11.000ns
Data Path Delay: 5.325ns (Levels of Logic = 1)
Clock Path Delay: 2.764ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Clock Path: in_pci_clock to pci/pci/initiator/enable
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
R7.I Tiopi 1.256 in_pci_clock
in_pci_clock
clock/pci/ibufg
in_pci_clock.DELAY_ADJ
BUFGMUX_X2Y1.I0 net (fanout=4) 0.296 clock_pci1
BUFGMUX_X2Y1.O Tgi0o 0.221 clock_pci_BUFG
clock_pci_BUFG
SLICE_X9Y52.CLK net (fanout=723) 0.991 clock_pci
------------------------------------------------- ---------------------------
Total 2.764ns (1.477ns logic, 1.287ns route)
(53.4% logic, 46.6% route)
Maximum Data Path: pci/pci/initiator/enable to out_pci_req
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y52.XQ Tcko 0.591 pci/pci/initiator/enable
pci/pci/initiator/enable
A5.O1 net (fanout=20) 1.493 pci/pci/initiator/enable
A5.PAD Tioop 3.241 out_pci_req
out_pci_req_OBUFT
out_pci_req
------------------------------------------------- ---------------------------
Total 5.325ns (3.832ns logic, 1.493ns route)
(72.0% logic, 28.0% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ts_in_0" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP
"in_ts_clock<0>";
4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 0.470ns.
--------------------------------------------------------------------------------
Slack: 2.030ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_valid<0> (PAD)
Destination: ts/io[0].io/ts_valid_0 (FF)
Destination Clock: clock_ts<0> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.265ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_valid<0> to ts/io[0].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B12.ICLK1 Tiopickd 2.735 in_ts_valid<0>
in_ts_valid<0>
in_ts_valid_0_IBUF
in_ts_valid<0>.DELAY_ADJ
ts/io[0].io/ts_valid_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 1.214 in_ts_clock<0>
in_ts_clock<0>
clock/ts/bit[0].ibufg
in_ts_clock<0>.DELAY_ADJ
BUFGMUX_X1Y10.I0 net (fanout=1) 0.027 clock_ts<0>1
BUFGMUX_X1Y10.O Tgi0o 0.199 clock_ts<0>_BUFG
clock_ts<0>_BUFG
B12.ICLK1 net (fanout=103) 0.825 clock_ts<0>
------------------------------------------------- ---------------------------
Total 2.265ns (1.413ns logic, 0.852ns route)
(62.4% logic, 37.6% route)
--------------------------------------------------------------------------------
Slack: 2.039ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_byte<0> (PAD)
Destination: ts/io[0].io/ts_byte_0 (FF)
Destination Clock: clock_ts<0> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.274ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_byte<0> to ts/io[0].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A13.ICLK1 Tiopickd 2.735 in_ts_byte<0>
in_ts_byte<0>
in_ts_byte_0_IBUF
in_ts_byte<0>.DELAY_ADJ
ts/io[0].io/ts_byte_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 1.214 in_ts_clock<0>
in_ts_clock<0>
clock/ts/bit[0].ibufg
in_ts_clock<0>.DELAY_ADJ
BUFGMUX_X1Y10.I0 net (fanout=1) 0.027 clock_ts<0>1
BUFGMUX_X1Y10.O Tgi0o 0.199 clock_ts<0>_BUFG
clock_ts<0>_BUFG
A13.ICLK1 net (fanout=103) 0.834 clock_ts<0>
------------------------------------------------- ---------------------------
Total 2.274ns (1.413ns logic, 0.861ns route)
(62.1% logic, 37.9% route)
--------------------------------------------------------------------------------
Slack: 2.039ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_data<0> (PAD)
Destination: ts/io[0].io/ts_data_0 (FF)
Destination Clock: clock_ts<0> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.274ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_data<0> to ts/io[0].io/ts_data_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A14.ICLK1 Tiopickd 2.735 in_ts_data<0>
in_ts_data<0>
in_ts_data_0_IBUF
in_ts_data<0>.DELAY_ADJ
ts/io[0].io/ts_data_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_data_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 1.214 in_ts_clock<0>
in_ts_clock<0>
clock/ts/bit[0].ibufg
in_ts_clock<0>.DELAY_ADJ
BUFGMUX_X1Y10.I0 net (fanout=1) 0.027 clock_ts<0>1
BUFGMUX_X1Y10.O Tgi0o 0.199 clock_ts<0>_BUFG
clock_ts<0>_BUFG
A14.ICLK1 net (fanout=103) 0.834 clock_ts<0>
------------------------------------------------- ---------------------------
Total 2.274ns (1.413ns logic, 0.861ns route)
(62.1% logic, 37.9% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ts_in_1" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP
"in_ts_clock<1>";
4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 0.470ns.
--------------------------------------------------------------------------------
Slack: 2.030ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_valid<1> (PAD)
Destination: ts/io[1].io/ts_valid_0 (FF)
Destination Clock: clock_ts<1> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.265ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_valid<1> to ts/io[1].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A12.ICLK2 Tiopickd 2.735 in_ts_valid<1>
in_ts_valid<1>
in_ts_valid_1_IBUF
in_ts_valid<1>.DELAY_ADJ
ts/io[1].io/ts_valid_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B8.I Tiopi 1.214 in_ts_clock<1>
in_ts_clock<1>
clock/ts/bit[1].ibufg
in_ts_clock<1>.DELAY_ADJ
BUFGMUX_X1Y11.I0 net (fanout=1) 0.027 clock_ts<1>1
BUFGMUX_X1Y11.O Tgi0o 0.199 clock_ts<1>_BUFG
clock_ts<1>_BUFG
A12.ICLK2 net (fanout=104) 0.825 clock_ts<1>
------------------------------------------------- ---------------------------
Total 2.265ns (1.413ns logic, 0.852ns route)
(62.4% logic, 37.6% route)
--------------------------------------------------------------------------------
Slack: 2.030ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_error<1> (PAD)
Destination: ts/io[1].io/ts_error_0 (FF)
Destination Clock: clock_ts<1> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.265ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_error<1> to ts/io[1].io/ts_error_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B6.ICLK1 Tiopickd 2.735 in_ts_error<1>
in_ts_error<1>
in_ts_error_1_IBUF
in_ts_error<1>.DELAY_ADJ
ts/io[1].io/ts_error_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_error_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B8.I Tiopi 1.214 in_ts_clock<1>
in_ts_clock<1>
clock/ts/bit[1].ibufg
in_ts_clock<1>.DELAY_ADJ
BUFGMUX_X1Y11.I0 net (fanout=1) 0.027 clock_ts<1>1
BUFGMUX_X1Y11.O Tgi0o 0.199 clock_ts<1>_BUFG
clock_ts<1>_BUFG
B6.ICLK1 net (fanout=104) 0.825 clock_ts<1>
------------------------------------------------- ---------------------------
Total 2.265ns (1.413ns logic, 0.852ns route)
(62.4% logic, 37.6% route)
--------------------------------------------------------------------------------
Slack: 2.030ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_byte<1> (PAD)
Destination: ts/io[1].io/ts_byte_0 (FF)
Destination Clock: clock_ts<1> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.265ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_byte<1> to ts/io[1].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A6.ICLK1 Tiopickd 2.735 in_ts_byte<1>
in_ts_byte<1>
in_ts_byte_1_IBUF
in_ts_byte<1>.DELAY_ADJ
ts/io[1].io/ts_byte_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B8.I Tiopi 1.214 in_ts_clock<1>
in_ts_clock<1>
clock/ts/bit[1].ibufg
in_ts_clock<1>.DELAY_ADJ
BUFGMUX_X1Y11.I0 net (fanout=1) 0.027 clock_ts<1>1
BUFGMUX_X1Y11.O Tgi0o 0.199 clock_ts<1>_BUFG
clock_ts<1>_BUFG
A6.ICLK1 net (fanout=104) 0.825 clock_ts<1>
------------------------------------------------- ---------------------------
Total 2.265ns (1.413ns logic, 0.852ns route)
(62.4% logic, 37.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ts_in_2" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP
"in_ts_clock<2>";
4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 0.457ns.
--------------------------------------------------------------------------------
Slack: 2.043ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_byte<2> (PAD)
Destination: ts/io[2].io/ts_byte_0 (FF)
Destination Clock: clock_ts<2> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.278ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_byte<2> to ts/io[2].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C12.ICLK1 Tiopickd 2.735 in_ts_byte<2>
in_ts_byte<2>
in_ts_byte_2_IBUF
in_ts_byte<2>.DELAY_ADJ
ts/io[2].io/ts_byte_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C10.I Tiopi 1.214 in_ts_clock<2>
in_ts_clock<2>
clock/ts/bit[2].ibufg
in_ts_clock<2>.DELAY_ADJ
BUFGMUX_X2Y10.I0 net (fanout=1) 0.027 clock_ts<2>1
BUFGMUX_X2Y10.O Tgi0o 0.199 clock_ts<2>_BUFG
clock_ts<2>_BUFG
C12.ICLK1 net (fanout=104) 0.838 clock_ts<2>
------------------------------------------------- ---------------------------
Total 2.278ns (1.413ns logic, 0.865ns route)
(62.0% logic, 38.0% route)
--------------------------------------------------------------------------------
Slack: 2.043ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_valid<2> (PAD)
Destination: ts/io[2].io/ts_valid_0 (FF)
Destination Clock: clock_ts<2> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.278ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_valid<2> to ts/io[2].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D11.ICLK1 Tiopickd 2.735 in_ts_valid<2>
in_ts_valid<2>
in_ts_valid_2_IBUF
in_ts_valid<2>.DELAY_ADJ
ts/io[2].io/ts_valid_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C10.I Tiopi 1.214 in_ts_clock<2>
in_ts_clock<2>
clock/ts/bit[2].ibufg
in_ts_clock<2>.DELAY_ADJ
BUFGMUX_X2Y10.I0 net (fanout=1) 0.027 clock_ts<2>1
BUFGMUX_X2Y10.O Tgi0o 0.199 clock_ts<2>_BUFG
clock_ts<2>_BUFG
D11.ICLK1 net (fanout=104) 0.838 clock_ts<2>
------------------------------------------------- ---------------------------
Total 2.278ns (1.413ns logic, 0.865ns route)
(62.0% logic, 38.0% route)
--------------------------------------------------------------------------------
Slack: 2.049ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_error<2> (PAD)
Destination: ts/io[2].io/ts_error_0 (FF)
Destination Clock: clock_ts<2> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.284ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_error<2> to ts/io[2].io/ts_error_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E14.ICLK1 Tiopickd 2.735 in_ts_error<2>
in_ts_error<2>
in_ts_error_2_IBUF
in_ts_error<2>.DELAY_ADJ
ts/io[2].io/ts_error_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_error_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C10.I Tiopi 1.214 in_ts_clock<2>
in_ts_clock<2>
clock/ts/bit[2].ibufg
in_ts_clock<2>.DELAY_ADJ
BUFGMUX_X2Y10.I0 net (fanout=1) 0.027 clock_ts<2>1
BUFGMUX_X2Y10.O Tgi0o 0.199 clock_ts<2>_BUFG
clock_ts<2>_BUFG
E14.ICLK1 net (fanout=104) 0.844 clock_ts<2>
------------------------------------------------- ---------------------------
Total 2.284ns (1.413ns logic, 0.871ns route)
(61.9% logic, 38.1% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ts_in_3" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP
"in_ts_clock<3>";
4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 0.466ns.
--------------------------------------------------------------------------------
Slack: 2.034ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_data<3> (PAD)
Destination: ts/io[3].io/ts_data_0 (FF)
Destination Clock: clock_ts<3> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.269ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_data<3> to ts/io[3].io/ts_data_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D10.ICLK1 Tiopickd 2.735 in_ts_data<3>
in_ts_data<3>
in_ts_data_3_IBUF
in_ts_data<3>.DELAY_ADJ
ts/io[3].io/ts_data_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_data_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D9.I Tiopi 1.214 in_ts_clock<3>
in_ts_clock<3>
clock/ts/bit[3].ibufg
in_ts_clock<3>.DELAY_ADJ
BUFGMUX_X2Y11.I0 net (fanout=1) 0.027 clock_ts<3>1
BUFGMUX_X2Y11.O Tgi0o 0.199 clock_ts<3>_BUFG
clock_ts<3>_BUFG
D10.ICLK1 net (fanout=104) 0.829 clock_ts<3>
------------------------------------------------- ---------------------------
Total 2.269ns (1.413ns logic, 0.856ns route)
(62.3% logic, 37.7% route)
--------------------------------------------------------------------------------
Slack: 2.046ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_valid<3> (PAD)
Destination: ts/io[3].io/ts_valid_0 (FF)
Destination Clock: clock_ts<3> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.281ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_valid<3> to ts/io[3].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C11.ICLK1 Tiopickd 2.735 in_ts_valid<3>
in_ts_valid<3>
in_ts_valid_3_IBUF
in_ts_valid<3>.DELAY_ADJ
ts/io[3].io/ts_valid_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_valid_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D9.I Tiopi 1.214 in_ts_clock<3>
in_ts_clock<3>
clock/ts/bit[3].ibufg
in_ts_clock<3>.DELAY_ADJ
BUFGMUX_X2Y11.I0 net (fanout=1) 0.027 clock_ts<3>1
BUFGMUX_X2Y11.O Tgi0o 0.199 clock_ts<3>_BUFG
clock_ts<3>_BUFG
C11.ICLK1 net (fanout=104) 0.841 clock_ts<3>
------------------------------------------------- ---------------------------
Total 2.281ns (1.413ns logic, 0.868ns route)
(61.9% logic, 38.1% route)
--------------------------------------------------------------------------------
Slack: 2.047ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: in_ts_byte<3> (PAD)
Destination: ts/io[3].io/ts_byte_0 (FF)
Destination Clock: clock_ts<3> rising at 0.000ns
Requirement: 2.500ns
Data Path Delay: 2.735ns (Levels of Logic = 0)
Clock Path Delay: 2.282ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: in_ts_byte<3> to ts/io[3].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B10.ICLK1 Tiopickd 2.735 in_ts_byte<3>
in_ts_byte<3>
in_ts_byte_3_IBUF
in_ts_byte<3>.DELAY_ADJ
ts/io[3].io/ts_byte_0
------------------------------------------------- ---------------------------
Total 2.735ns (2.735ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_byte_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D9.I Tiopi 1.214 in_ts_clock<3>
in_ts_clock<3>
clock/ts/bit[3].ibufg
in_ts_clock<3>.DELAY_ADJ
BUFGMUX_X2Y11.I0 net (fanout=1) 0.027 clock_ts<3>1
BUFGMUX_X2Y11.O Tgi0o 0.199 clock_ts<3>_BUFG
clock_ts<3>_BUFG
B10.ICLK1 net (fanout=104) 0.842 clock_ts<3>
------------------------------------------------- ---------------------------
Total 2.282ns (1.413ns logic, 0.869ns route)
(61.9% logic, 38.1% route)
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_pci_clock
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_pci_clock | 30.000ns| 13.902ns| 27.858ns| 0| 0| 21513| 6551|
| TS_clock_pci_ram_clock | 10.000ns| 9.286ns| N/A| 0| 0| 6551| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock in_pci_clock
-------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------+------------+------------+------------------+--------+
in_pci_gnt | 8.202(R)| -1.452(R)|clock_pci | 0.000|
in_pci_idsel | 4.641(R)| -1.215(R)|clock_pci | 0.000|
io_pci_ad<0> | 4.705(R)| -1.290(R)|clock_pci | 0.000|
io_pci_ad<1> | 4.708(R)| -1.294(R)|clock_pci | 0.000|
io_pci_ad<2> | 4.705(R)| -1.290(R)|clock_pci | 0.000|
io_pci_ad<3> | 4.708(R)| -1.294(R)|clock_pci | 0.000|
io_pci_ad<4> | 4.741(R)| -1.333(R)|clock_pci | 0.000|
io_pci_ad<5> | 4.715(R)| -1.301(R)|clock_pci | 0.000|
io_pci_ad<6> | 4.741(R)| -1.333(R)|clock_pci | 0.000|
io_pci_ad<7> | 4.715(R)| -1.301(R)|clock_pci | 0.000|
io_pci_ad<8> | 4.734(R)| -1.324(R)|clock_pci | 0.000|
io_pci_ad<9> | 4.730(R)| -1.320(R)|clock_pci | 0.000|
io_pci_ad<10>| 4.734(R)| -1.324(R)|clock_pci | 0.000|
io_pci_ad<11>| 4.707(R)| -1.292(R)|clock_pci | 0.000|
io_pci_ad<12>| 4.710(R)| -1.296(R)|clock_pci | 0.000|
io_pci_ad<13>| 4.722(R)| -1.310(R)|clock_pci | 0.000|
io_pci_ad<14>| 4.710(R)| -1.296(R)|clock_pci | 0.000|
io_pci_ad<15>| 4.736(R)| -1.326(R)|clock_pci | 0.000|
io_pci_ad<16>| 4.753(R)| -1.347(R)|clock_pci | 0.000|
io_pci_ad<17>| 4.692(R)| -1.275(R)|clock_pci | 0.000|
io_pci_ad<18>| 4.682(R)| -1.263(R)|clock_pci | 0.000|
io_pci_ad<19>| 4.730(R)| -1.319(R)|clock_pci | 0.000|
io_pci_ad<20>| 4.730(R)| -1.319(R)|clock_pci | 0.000|
io_pci_ad<21>| 4.692(R)| -1.275(R)|clock_pci | 0.000|
io_pci_ad<22>| 4.682(R)| -1.263(R)|clock_pci | 0.000|
io_pci_ad<23>| 4.675(R)| -1.255(R)|clock_pci | 0.000|
io_pci_ad<24>| 4.764(R)| -1.359(R)|clock_pci | 0.000|
io_pci_ad<25>| 4.620(R)| -1.190(R)|clock_pci | 0.000|
io_pci_ad<26>| 4.664(R)| -1.242(R)|clock_pci | 0.000|
io_pci_ad<27>| 4.620(R)| -1.190(R)|clock_pci | 0.000|
io_pci_ad<28>| 4.765(R)| -1.361(R)|clock_pci | 0.000|
io_pci_ad<29>| 4.741(R)| -1.333(R)|clock_pci | 0.000|
io_pci_ad<30>| 4.765(R)| -1.361(R)|clock_pci | 0.000|
io_pci_ad<31>| 4.741(R)| -1.333(R)|clock_pci | 0.000|
io_pci_cbe<0>| 4.730(R)| -1.320(R)|clock_pci | 0.000|
io_pci_cbe<1>| 4.707(R)| -1.292(R)|clock_pci | 0.000|
io_pci_cbe<2>| 4.750(R)| -1.343(R)|clock_pci | 0.000|
io_pci_cbe<3>| 4.773(R)| -1.255(R)|clock_pci | 0.000|
io_pci_devsel| 5.911(R)| -0.349(R)|clock_pci | 0.000|
io_pci_frame | 5.472(R)| -0.201(R)|clock_pci | 0.000|
io_pci_irdy | 5.554(R)| -0.435(R)|clock_pci | 0.000|
io_pci_stop | 5.934(R)| -0.369(R)|clock_pci | 0.000|
io_pci_trdy | 5.981(R)| -0.327(R)|clock_pci | 0.000|
-------------+------------+------------+------------------+--------+
Setup/Hold to clock in_ts_clock<0>
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
in_ts_byte<0> | 0.461(R)| 0.524(R)|clock_ts<0> | 0.000|
in_ts_data<0> | 0.461(R)| 0.524(R)|clock_ts<0> | 0.000|
in_ts_error<0>| 0.435(R)| 0.554(R)|clock_ts<0> | 0.000|
in_ts_valid<0>| 0.470(R)| 0.514(R)|clock_ts<0> | 0.000|
--------------+------------+------------+------------------+--------+
Setup/Hold to clock in_ts_clock<1>
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
in_ts_byte<1> | 0.470(R)| 0.514(R)|clock_ts<1> | 0.000|
in_ts_data<1> | 0.455(R)| 0.531(R)|clock_ts<1> | 0.000|
in_ts_error<1>| 0.470(R)| 0.514(R)|clock_ts<1> | 0.000|
in_ts_valid<1>| 0.470(R)| 0.514(R)|clock_ts<1> | 0.000|
--------------+------------+------------+------------------+--------+
Setup/Hold to clock in_ts_clock<2>
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
in_ts_byte<2> | 0.457(R)| 0.529(R)|clock_ts<2> | 0.000|
in_ts_data<2> | 0.446(R)| 0.542(R)|clock_ts<2> | 0.000|
in_ts_error<2>| 0.451(R)| 0.536(R)|clock_ts<2> | 0.000|
in_ts_valid<2>| 0.457(R)| 0.529(R)|clock_ts<2> | 0.000|
--------------+------------+------------+------------------+--------+
Setup/Hold to clock in_ts_clock<3>
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
in_ts_byte<3> | 0.453(R)| 0.533(R)|clock_ts<3> | 0.000|
in_ts_data<3> | 0.466(R)| 0.518(R)|clock_ts<3> | 0.000|
in_ts_error<3>| 0.453(R)| 0.534(R)|clock_ts<3> | 0.000|
in_ts_valid<3>| 0.454(R)| 0.533(R)|clock_ts<3> | 0.000|
--------------+------------+------------+------------------+--------+
Clock in_pci_clock to Pad
-------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
-------------+------------+------------------+--------+
io_pci_ad<0> | 9.365(R)|clock_pci | 0.000|
io_pci_ad<1> | 8.990(R)|clock_pci | 0.000|
io_pci_ad<2> | 9.475(R)|clock_pci | 0.000|
io_pci_ad<3> | 8.735(R)|clock_pci | 0.000|
io_pci_ad<4> | 8.753(R)|clock_pci | 0.000|
io_pci_ad<5> | 9.020(R)|clock_pci | 0.000|
io_pci_ad<6> | 8.885(R)|clock_pci | 0.000|
io_pci_ad<7> | 9.285(R)|clock_pci | 0.000|
io_pci_ad<8> | 9.028(R)|clock_pci | 0.000|
io_pci_ad<9> | 9.309(R)|clock_pci | 0.000|
io_pci_ad<10>| 8.994(R)|clock_pci | 0.000|
io_pci_ad<11>| 9.856(R)|clock_pci | 0.000|
io_pci_ad<12>| 8.298(R)|clock_pci | 0.000|
io_pci_ad<13>| 9.314(R)|clock_pci | 0.000|
io_pci_ad<14>| 9.587(R)|clock_pci | 0.000|
io_pci_ad<15>| 8.180(R)|clock_pci | 0.000|
io_pci_ad<16>| 8.972(R)|clock_pci | 0.000|
io_pci_ad<17>| 8.796(R)|clock_pci | 0.000|
io_pci_ad<18>| 9.305(R)|clock_pci | 0.000|
io_pci_ad<19>| 8.269(R)|clock_pci | 0.000|
io_pci_ad<20>| 8.764(R)|clock_pci | 0.000|
io_pci_ad<21>| 9.010(R)|clock_pci | 0.000|
io_pci_ad<22>| 8.508(R)|clock_pci | 0.000|
io_pci_ad<23>| 8.869(R)|clock_pci | 0.000|
io_pci_ad<24>| 8.329(R)|clock_pci | 0.000|
io_pci_ad<25>| 8.557(R)|clock_pci | 0.000|
io_pci_ad<26>| 9.134(R)|clock_pci | 0.000|
io_pci_ad<27>| 8.879(R)|clock_pci | 0.000|
io_pci_ad<28>| 8.358(R)|clock_pci | 0.000|
io_pci_ad<29>| 8.849(R)|clock_pci | 0.000|
io_pci_ad<30>| 9.436(R)|clock_pci | 0.000|
io_pci_ad<31>| 8.598(R)|clock_pci | 0.000|
io_pci_cbe<0>| 8.524(R)|clock_pci | 0.000|
io_pci_cbe<1>| 8.822(R)|clock_pci | 0.000|
io_pci_cbe<2>| 7.322(R)|clock_pci | 0.000|
io_pci_cbe<3>| 8.436(R)|clock_pci | 0.000|
io_pci_devsel| 7.686(R)|clock_pci | 0.000|
io_pci_frame | 7.623(R)|clock_pci | 0.000|
io_pci_irdy | 7.647(R)|clock_pci | 0.000|
io_pci_stop | 7.752(R)|clock_pci | 0.000|
io_pci_trdy | 7.845(R)|clock_pci | 0.000|
out_pci_par | 7.395(R)|clock_pci | 0.000|
out_pci_req | 8.089(R)|clock_pci | 0.000|
-------------+------------+------------------+--------+
Clock to Setup on destination clock in_pci_clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_pci_clock | 13.902| | 1.806| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_ts_clock<0>
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<0> | 6.433| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_ts_clock<1>
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<1> | 6.700| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_ts_clock<2>
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<2> | 6.601| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_ts_clock<3>
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<3> | 7.804| | | |
---------------+---------+---------+---------+---------+
TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 5.780; Ideal Clock Offset To Actual Clock -0.009;
-------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-------------+------------+------------+---------+---------+-------------+
in_pci_idsel | 4.641(R)| -1.215(R)| 1.359| 1.015| 0.172|
io_pci_ad<0> | 4.705(R)| -1.290(R)| 1.295| 1.090| 0.102|
io_pci_ad<1> | 4.708(R)| -1.294(R)| 1.292| 1.094| 0.099|
io_pci_ad<2> | 4.705(R)| -1.290(R)| 1.295| 1.090| 0.102|
io_pci_ad<3> | 4.708(R)| -1.294(R)| 1.292| 1.094| 0.099|
io_pci_ad<4> | 4.741(R)| -1.333(R)| 1.259| 1.133| 0.063|
io_pci_ad<5> | 4.715(R)| -1.301(R)| 1.285| 1.101| 0.092|
io_pci_ad<6> | 4.741(R)| -1.333(R)| 1.259| 1.133| 0.063|
io_pci_ad<7> | 4.715(R)| -1.301(R)| 1.285| 1.101| 0.092|
io_pci_ad<8> | 4.734(R)| -1.324(R)| 1.266| 1.124| 0.071|
io_pci_ad<9> | 4.730(R)| -1.320(R)| 1.270| 1.120| 0.075|
io_pci_ad<10>| 4.734(R)| -1.324(R)| 1.266| 1.124| 0.071|
io_pci_ad<11>| 4.707(R)| -1.292(R)| 1.293| 1.092| 0.100|
io_pci_ad<12>| 4.710(R)| -1.296(R)| 1.290| 1.096| 0.097|
io_pci_ad<13>| 4.722(R)| -1.310(R)| 1.278| 1.110| 0.084|
io_pci_ad<14>| 4.710(R)| -1.296(R)| 1.290| 1.096| 0.097|
io_pci_ad<15>| 4.736(R)| -1.326(R)| 1.264| 1.126| 0.069|
io_pci_ad<16>| 4.753(R)| -1.347(R)| 1.247| 1.147| 0.050|
io_pci_ad<17>| 4.692(R)| -1.275(R)| 1.308| 1.075| 0.117|
io_pci_ad<18>| 4.682(R)| -1.263(R)| 1.318| 1.063| 0.128|
io_pci_ad<19>| 4.730(R)| -1.319(R)| 1.270| 1.119| 0.076|
io_pci_ad<20>| 4.730(R)| -1.319(R)| 1.270| 1.119| 0.076|
io_pci_ad<21>| 4.692(R)| -1.275(R)| 1.308| 1.075| 0.117|
io_pci_ad<22>| 4.682(R)| -1.263(R)| 1.318| 1.063| 0.128|
io_pci_ad<23>| 4.675(R)| -1.255(R)| 1.325| 1.055| 0.135|
io_pci_ad<24>| 4.764(R)| -1.359(R)| 1.236| 1.159| 0.038|
io_pci_ad<25>| 4.620(R)| -1.190(R)| 1.380| 0.990| 0.195|
io_pci_ad<26>| 4.664(R)| -1.242(R)| 1.336| 1.042| 0.147|
io_pci_ad<27>| 4.620(R)| -1.190(R)| 1.380| 0.990| 0.195|
io_pci_ad<28>| 4.765(R)| -1.361(R)| 1.235| 1.161| 0.037|
io_pci_ad<29>| 4.741(R)| -1.333(R)| 1.259| 1.133| 0.063|
io_pci_ad<30>| 4.765(R)| -1.361(R)| 1.235| 1.161| 0.037|
io_pci_ad<31>| 4.741(R)| -1.333(R)| 1.259| 1.133| 0.063|
io_pci_cbe<0>| 4.730(R)| -1.320(R)| 1.270| 1.120| 0.075|
io_pci_cbe<1>| 4.707(R)| -1.292(R)| 1.293| 1.092| 0.100|
io_pci_cbe<2>| 4.750(R)| -1.343(R)| 1.250| 1.143| 0.053|
io_pci_cbe<3>| 4.773(R)| -1.255(R)| 1.227| 1.055| 0.086|
io_pci_devsel| 5.911(R)| -0.349(R)| 0.089| 0.149| -0.030|
io_pci_frame | 5.472(R)| -0.201(R)| 0.528| 0.001| 0.264|
io_pci_irdy | 5.554(R)| -0.435(R)| 0.446| 0.235| 0.106|
io_pci_stop | 5.934(R)| -0.369(R)| 0.066| 0.169| -0.052|
io_pci_trdy | 5.981(R)| -0.327(R)| 0.019| 0.127| -0.054|
-------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 5.981| -0.201| 0.019| 0.001| |
-------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 6.750; Ideal Clock Offset To Actual Clock 0.227;
------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
------------+------------+------------+---------+---------+-------------+
in_pci_gnt | 8.202(R)| -1.452(R)| 0.798| 1.252| -0.227|
------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 8.202| -1.452| 0.798| 1.252| |
------------+------------+------------+---------+---------+-------------+
TIMEGRP "ts_in_0" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP "in_ts_clock<0>";
Worst Case Data Window 1.024; Ideal Clock Offset To Actual Clock -0.042;
--------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<0> | 0.461(R)| 0.524(R)| 2.039| 1.976| 0.032|
in_ts_data<0> | 0.461(R)| 0.524(R)| 2.039| 1.976| 0.032|
in_ts_error<0>| 0.435(R)| 0.554(R)| 2.065| 1.946| 0.060|
in_ts_valid<0>| 0.470(R)| 0.514(R)| 2.030| 1.986| 0.022|
--------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 0.470| 0.554| 2.030| 1.946| |
--------------+------------+------------+---------+---------+-------------+
TIMEGRP "ts_in_1" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP "in_ts_clock<1>";
Worst Case Data Window 1.001; Ideal Clock Offset To Actual Clock -0.030;
--------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<1> | 0.470(R)| 0.514(R)| 2.030| 1.986| 0.022|
in_ts_data<1> | 0.455(R)| 0.531(R)| 2.045| 1.969| 0.038|
in_ts_error<1>| 0.470(R)| 0.514(R)| 2.030| 1.986| 0.022|
in_ts_valid<1>| 0.470(R)| 0.514(R)| 2.030| 1.986| 0.022|
--------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 0.470| 0.531| 2.030| 1.969| |
--------------+------------+------------+---------+---------+-------------+
TIMEGRP "ts_in_2" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP "in_ts_clock<2>";
Worst Case Data Window 0.999; Ideal Clock Offset To Actual Clock -0.043;
--------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<2> | 0.457(R)| 0.529(R)| 2.043| 1.971| 0.036|
in_ts_data<2> | 0.446(R)| 0.542(R)| 2.054| 1.958| 0.048|
in_ts_error<2>| 0.451(R)| 0.536(R)| 2.049| 1.964| 0.042|
in_ts_valid<2>| 0.457(R)| 0.529(R)| 2.043| 1.971| 0.036|
--------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 0.457| 0.542| 2.043| 1.958| |
--------------+------------+------------+---------+---------+-------------+
TIMEGRP "ts_in_3" OFFSET = IN 2.5 ns VALID 5 ns BEFORE COMP "in_ts_clock<3>";
Worst Case Data Window 1.000; Ideal Clock Offset To Actual Clock -0.034;
--------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<3> | 0.453(R)| 0.533(R)| 2.047| 1.967| 0.040|
in_ts_data<3> | 0.466(R)| 0.518(R)| 2.034| 1.982| 0.026|
in_ts_error<3>| 0.453(R)| 0.534(R)| 2.047| 1.966| 0.041|
in_ts_valid<3>| 0.454(R)| 0.533(R)| 2.046| 1.967| 0.039|
--------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 0.466| 0.534| 2.034| 1.966| |
--------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP "in_pci_clock";
Bus Skew: 2.534 ns;
-----------------------------------------------+-------------+-------------+
PAD | Delay (ns) |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
io_pci_ad<0> | 9.365| 2.043|
io_pci_ad<1> | 8.990| 1.668|
io_pci_ad<2> | 9.475| 2.153|
io_pci_ad<3> | 8.735| 1.413|
io_pci_ad<4> | 8.753| 1.431|
io_pci_ad<5> | 9.020| 1.698|
io_pci_ad<6> | 8.885| 1.563|
io_pci_ad<7> | 9.285| 1.963|
io_pci_ad<8> | 9.028| 1.706|
io_pci_ad<9> | 9.309| 1.987|
io_pci_ad<10> | 8.994| 1.672|
io_pci_ad<11> | 9.856| 2.534|
io_pci_ad<12> | 8.298| 0.976|
io_pci_ad<13> | 9.314| 1.992|
io_pci_ad<14> | 9.587| 2.265|
io_pci_ad<15> | 8.180| 0.858|
io_pci_ad<16> | 8.972| 1.650|
io_pci_ad<17> | 8.796| 1.474|
io_pci_ad<18> | 9.305| 1.983|
io_pci_ad<19> | 8.269| 0.947|
io_pci_ad<20> | 8.764| 1.442|
io_pci_ad<21> | 9.010| 1.688|
io_pci_ad<22> | 8.508| 1.186|
io_pci_ad<23> | 8.869| 1.547|
io_pci_ad<24> | 8.329| 1.007|
io_pci_ad<25> | 8.557| 1.235|
io_pci_ad<26> | 9.134| 1.812|
io_pci_ad<27> | 8.879| 1.557|
io_pci_ad<28> | 8.358| 1.036|
io_pci_ad<29> | 8.849| 1.527|
io_pci_ad<30> | 9.436| 2.114|
io_pci_ad<31> | 8.598| 1.276|
io_pci_cbe<0> | 8.524| 1.202|
io_pci_cbe<1> | 8.822| 1.500|
io_pci_cbe<2> | 7.322| 0.000|
io_pci_cbe<3> | 8.436| 1.114|
io_pci_devsel | 7.686| 0.364|
io_pci_frame | 7.623| 0.301|
io_pci_irdy | 7.647| 0.325|
io_pci_stop | 7.752| 0.430|
io_pci_trdy | 7.845| 0.523|
out_pci_par | 7.395| 0.073|
-----------------------------------------------+-------------+-------------+
TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP "in_pci_clock";
Bus Skew: 0.000 ns;
-----------------------------------------------+-------------+-------------+
PAD | Delay (ns) |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
out_pci_req | 8.089| 0.000|
-----------------------------------------------+-------------+-------------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 34375 paths, 0 nets, and 10785 connections
Design statistics:
Minimum period: 13.902ns{1} (Maximum frequency: 71.932MHz)
Minimum input required time before clock: 8.202ns
Minimum output required time after clock: 9.856ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed SUN 13 SEP 0:23:16 2009
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 150 MB