トップPT1/PT2スタティック タイミング レポート

PT1 リリース番号: 01

--------------------------------------------------------------------------------
Release 10.1.03 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

E:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise E:/RTL/Project/PT1/PT1.ise
-intstyle ise -v 3 -s 4 -xml PT1 PT1.ncd -o PT1.twr PT1.pcf -ucf
E:/RTL/Code/PT1/UCF/PT1.ucf

Design file:              PT1.ncd
Physical constraint file: PT1.pcf
Device,package,speed:     xc3s200a,ft256,-4 (PRODUCTION 1.41 2008-07-25)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%;

 21466 paths analyzed, 3316 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  16.608ns.
--------------------------------------------------------------------------------
Slack:                  7.057ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_7 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_7 (FF)
  Requirement:          10.000ns
  Data Path Delay:      5.019ns (Levels of Logic = 0)
  Clock Path Skew:      2.076ns (1.304 - -0.772)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_7 to fifo/fifo/count/write_address_gray_0_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y35.XQ      Tcko                  0.591   fifo/fifo/write/out_gray<7>
                                                       fifo/fifo/write/out_gray_7
    SLICE_X24Y34.BX      net (fanout=1)        4.085   fifo/fifo/write/out_gray<7>
    SLICE_X24Y34.CLK     Tdick                 0.343   fifo/fifo/count/write_address_gray_0_7
                                                       fifo/fifo/count/write_address_gray_0_7
    -------------------------------------------------  ---------------------------
    Total                                      5.019ns (0.934ns logic, 4.085ns route)
                                                       (18.6% logic, 81.4% route)

--------------------------------------------------------------------------------
Slack:                  7.269ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_8 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_8 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.732ns (Levels of Logic = 0)
  Clock Path Skew:      2.001ns (1.210 - -0.791)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_8 to fifo/fifo/count/write_address_gray_0_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y45.YQ      Tcko                  0.580   fifo/fifo/write/out_gray<9>
                                                       fifo/fifo/write/out_gray_8
    SLICE_X26Y45.BY      net (fanout=1)        3.766   fifo/fifo/write/out_gray<8>
    SLICE_X26Y45.CLK     Tdick                 0.386   fifo/fifo/count/write_address_gray_0_9
                                                       fifo/fifo/count/write_address_gray_0_8
    -------------------------------------------------  ---------------------------
    Total                                      4.732ns (0.966ns logic, 3.766ns route)
                                                       (20.4% logic, 79.6% route)

--------------------------------------------------------------------------------
Slack:                  7.281ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_9 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_9 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.720ns (Levels of Logic = 0)
  Clock Path Skew:      2.001ns (1.210 - -0.791)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_9 to fifo/fifo/count/write_address_gray_0_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y45.XQ      Tcko                  0.591   fifo/fifo/write/out_gray<9>
                                                       fifo/fifo/write/out_gray_9
    SLICE_X26Y45.BX      net (fanout=1)        3.786   fifo/fifo/write/out_gray<9>
    SLICE_X26Y45.CLK     Tdick                 0.343   fifo/fifo/count/write_address_gray_0_9
                                                       fifo/fifo/count/write_address_gray_0_9
    -------------------------------------------------  ---------------------------
    Total                                      4.720ns (0.934ns logic, 3.786ns route)
                                                       (19.8% logic, 80.2% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ts_clock_0 = PERIOD TIMEGRP "ts_clock_0" 15.2 ns HIGH 
50%;

 1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.481ns.
--------------------------------------------------------------------------------
Slack:                  8.719ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[0].packet/a_count_l (FF)
  Destination:          ts/packet[0].packet/out_data_26 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.363ns (Levels of Logic = 3)
  Clock Path Skew:      -0.118ns (0.531 - 0.649)
  Source Clock:         clock_ts<0> rising at 0.000ns
  Destination Clock:    clock_ts<0> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[0].packet/a_count_l to ts/packet[0].packet/out_data_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y29.YQ      Tcko                  0.580   ts/packet[0].packet/b_count_l
                                                       ts/packet[0].packet/a_count_l
    SLICE_X13Y17.G2      net (fanout=7)        1.678   ts/packet[0].packet/a_count_l
    SLICE_X13Y17.Y       Tilo                  0.648   ts/packet[0].packet/N9
                                                       ts/packet[0].packet/out_data_mux0000<10>11
    SLICE_X13Y16.G4      net (fanout=3)        0.130   ts/packet[0].packet/N1
    SLICE_X13Y16.Y       Tilo                  0.648   ts/packet[0].packet/out_data<24>
                                                       ts/packet[0].packet/out_data_mux0000<1>21
    SLICE_X4Y11.G4       net (fanout=6)        1.862   ts/packet[0].packet/N14
    SLICE_X4Y11.CLK      Tgck                  0.817   ts/packet[0].packet/out_data<27>
                                                       ts/packet[0].packet/out_data_mux0000<5>1
                                                       ts/packet[0].packet/out_data_26
    -------------------------------------------------  ---------------------------
    Total                                      6.363ns (2.693ns logic, 3.670ns route)
                                                       (42.3% logic, 57.7% route)

--------------------------------------------------------------------------------
Slack:                  8.854ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[0].packet/a_count_l (FF)
  Destination:          ts/packet[0].packet/out_data_15 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.245ns (Levels of Logic = 3)
  Clock Path Skew:      -0.101ns (0.548 - 0.649)
  Source Clock:         clock_ts<0> rising at 0.000ns
  Destination Clock:    clock_ts<0> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[0].packet/a_count_l to ts/packet[0].packet/out_data_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y29.YQ      Tcko                  0.580   ts/packet[0].packet/b_count_l
                                                       ts/packet[0].packet/a_count_l
    SLICE_X13Y17.G2      net (fanout=7)        1.678   ts/packet[0].packet/a_count_l
    SLICE_X13Y17.Y       Tilo                  0.648   ts/packet[0].packet/N9
                                                       ts/packet[0].packet/out_data_mux0000<10>11
    SLICE_X13Y17.F4      net (fanout=3)        0.128   ts/packet[0].packet/N1
    SLICE_X13Y17.X       Tilo                  0.643   ts/packet[0].packet/N9
                                                       ts/packet[0].packet/out_data_mux0000<10>21
    SLICE_X7Y10.F2       net (fanout=19)       1.846   ts/packet[0].packet/N9
    SLICE_X7Y10.CLK      Tfck                  0.722   ts/packet[0].packet/out_data<15>
                                                       ts/packet[0].packet/out_data_mux0000<16>1
                                                       ts/packet[0].packet/out_data_15
    -------------------------------------------------  ---------------------------
    Total                                      6.245ns (2.593ns logic, 3.652ns route)
                                                       (41.5% logic, 58.5% route)

--------------------------------------------------------------------------------
Slack:                  8.867ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[0].packet/a_count_l (FF)
  Destination:          ts/packet[0].packet/out_data_23 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.232ns (Levels of Logic = 3)
  Clock Path Skew:      -0.101ns (0.548 - 0.649)
  Source Clock:         clock_ts<0> rising at 0.000ns
  Destination Clock:    clock_ts<0> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[0].packet/a_count_l to ts/packet[0].packet/out_data_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y29.YQ      Tcko                  0.580   ts/packet[0].packet/b_count_l
                                                       ts/packet[0].packet/a_count_l
    SLICE_X13Y17.G2      net (fanout=7)        1.678   ts/packet[0].packet/a_count_l
    SLICE_X13Y17.Y       Tilo                  0.648   ts/packet[0].packet/N9
                                                       ts/packet[0].packet/out_data_mux0000<10>11
    SLICE_X13Y17.F4      net (fanout=3)        0.128   ts/packet[0].packet/N1
    SLICE_X13Y17.X       Tilo                  0.643   ts/packet[0].packet/N9
                                                       ts/packet[0].packet/out_data_mux0000<10>21
    SLICE_X7Y11.G2       net (fanout=19)       1.828   ts/packet[0].packet/N9
    SLICE_X7Y11.CLK      Tgck                  0.727   ts/packet[0].packet/out_data<23>
                                                       ts/packet[0].packet/out_data_mux0000<8>1
                                                       ts/packet[0].packet/out_data_23
    -------------------------------------------------  ---------------------------
    Total                                      6.232ns (2.598ns logic, 3.634ns route)
                                                       (41.7% logic, 58.3% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ts_clock_1 = PERIOD TIMEGRP "ts_clock_1" 24.4 ns HIGH 
50%;

 1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.721ns.
--------------------------------------------------------------------------------
Slack:                  17.679ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[1].packet/a_count_l (FF)
  Destination:          ts/packet[1].packet/count_2 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.639ns (Levels of Logic = 3)
  Clock Path Skew:      -0.082ns (0.210 - 0.292)
  Source Clock:         clock_ts<1> rising at 0.000ns
  Destination Clock:    clock_ts<1> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[1].packet/a_count_l to ts/packet[1].packet/count_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y28.YQ      Tcko                  0.676   ts/packet[1].packet/b_count_l
                                                       ts/packet[1].packet/a_count_l
    SLICE_X6Y22.G1       net (fanout=7)        1.494   ts/packet[1].packet/a_count_l
    SLICE_X6Y22.Y        Tilo                  0.707   ts/packet[1].packet/N9
                                                       ts/packet[1].packet/out_data_mux0000<10>11
    SLICE_X6Y21.G2       net (fanout=3)        0.474   ts/packet[1].packet/N1
    SLICE_X6Y21.Y        Tilo                  0.707   ts/packet[1].packet/out_data<24>
                                                       ts/packet[1].packet/out_data_mux0000<1>21
    SLICE_X7Y18.F3       net (fanout=6)        0.475   ts/packet[1].packet/N14
    SLICE_X7Y18.X        Tilo                  0.643   ts/packet[1].packet/out_data<25>
                                                       ts/packet[1].packet/count_not00011
    SLICE_X6Y16.CE       net (fanout=2)        1.152   ts/packet[1].packet/count_not0001
    SLICE_X6Y16.CLK      Tceck                 0.311   ts/packet[1].packet/count<2>
                                                       ts/packet[1].packet/count_2
    -------------------------------------------------  ---------------------------
    Total                                      6.639ns (3.044ns logic, 3.595ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------
Slack:                  17.679ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[1].packet/a_count_l (FF)
  Destination:          ts/packet[1].packet/count_1 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.639ns (Levels of Logic = 3)
  Clock Path Skew:      -0.082ns (0.210 - 0.292)
  Source Clock:         clock_ts<1> rising at 0.000ns
  Destination Clock:    clock_ts<1> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[1].packet/a_count_l to ts/packet[1].packet/count_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y28.YQ      Tcko                  0.676   ts/packet[1].packet/b_count_l
                                                       ts/packet[1].packet/a_count_l
    SLICE_X6Y22.G1       net (fanout=7)        1.494   ts/packet[1].packet/a_count_l
    SLICE_X6Y22.Y        Tilo                  0.707   ts/packet[1].packet/N9
                                                       ts/packet[1].packet/out_data_mux0000<10>11
    SLICE_X6Y21.G2       net (fanout=3)        0.474   ts/packet[1].packet/N1
    SLICE_X6Y21.Y        Tilo                  0.707   ts/packet[1].packet/out_data<24>
                                                       ts/packet[1].packet/out_data_mux0000<1>21
    SLICE_X7Y18.F3       net (fanout=6)        0.475   ts/packet[1].packet/N14
    SLICE_X7Y18.X        Tilo                  0.643   ts/packet[1].packet/out_data<25>
                                                       ts/packet[1].packet/count_not00011
    SLICE_X6Y17.CE       net (fanout=2)        1.152   ts/packet[1].packet/count_not0001
    SLICE_X6Y17.CLK      Tceck                 0.311   ts/packet[1].packet/count<0>
                                                       ts/packet[1].packet/count_1
    -------------------------------------------------  ---------------------------
    Total                                      6.639ns (3.044ns logic, 3.595ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------
Slack:                  17.679ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[1].packet/a_count_l (FF)
  Destination:          ts/packet[1].packet/count_0 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.639ns (Levels of Logic = 3)
  Clock Path Skew:      -0.082ns (0.210 - 0.292)
  Source Clock:         clock_ts<1> rising at 0.000ns
  Destination Clock:    clock_ts<1> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[1].packet/a_count_l to ts/packet[1].packet/count_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y28.YQ      Tcko                  0.676   ts/packet[1].packet/b_count_l
                                                       ts/packet[1].packet/a_count_l
    SLICE_X6Y22.G1       net (fanout=7)        1.494   ts/packet[1].packet/a_count_l
    SLICE_X6Y22.Y        Tilo                  0.707   ts/packet[1].packet/N9
                                                       ts/packet[1].packet/out_data_mux0000<10>11
    SLICE_X6Y21.G2       net (fanout=3)        0.474   ts/packet[1].packet/N1
    SLICE_X6Y21.Y        Tilo                  0.707   ts/packet[1].packet/out_data<24>
                                                       ts/packet[1].packet/out_data_mux0000<1>21
    SLICE_X7Y18.F3       net (fanout=6)        0.475   ts/packet[1].packet/N14
    SLICE_X7Y18.X        Tilo                  0.643   ts/packet[1].packet/out_data<25>
                                                       ts/packet[1].packet/count_not00011
    SLICE_X6Y17.CE       net (fanout=2)        1.152   ts/packet[1].packet/count_not0001
    SLICE_X6Y17.CLK      Tceck                 0.311   ts/packet[1].packet/count<0>
                                                       ts/packet[1].packet/count_0
    -------------------------------------------------  ---------------------------
    Total                                      6.639ns (3.044ns logic, 3.595ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ts_clock_2 = PERIOD TIMEGRP "ts_clock_2" 15.2 ns HIGH 
50%;

 1204 paths analyzed, 556 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.680ns.
--------------------------------------------------------------------------------
Slack:                  8.520ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/enable__[2].enable_/out_enable (FF)
  Destination:          ts/error[2].error/binary_21 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.661ns (Levels of Logic = 1)
  Clock Path Skew:      -0.019ns (0.627 - 0.646)
  Source Clock:         clock_ts<2> rising at 0.000ns
  Destination Clock:    clock_ts<2> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/enable__[2].enable_/out_enable to ts/error[2].error/binary_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y20.YQ      Tcko                  0.580   ts/enable__[2].enable_/out_enable
                                                       ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.G3      net (fanout=72)       2.686   ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.Y       Tilo                  0.707   ts/error[2].error/binary_not0001
                                                       ts/error[2].error/binary_not00011
    SLICE_X25Y58.CE      net (fanout=12)       2.377   ts/error[2].error/binary_not0001
    SLICE_X25Y58.CLK     Tceck                 0.311   ts/error[2].error/binary<20>
                                                       ts/error[2].error/binary_21
    -------------------------------------------------  ---------------------------
    Total                                      6.661ns (1.598ns logic, 5.063ns route)
                                                       (24.0% logic, 76.0% route)

--------------------------------------------------------------------------------
Slack:                  8.520ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/enable__[2].enable_/out_enable (FF)
  Destination:          ts/error[2].error/binary_23 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.661ns (Levels of Logic = 1)
  Clock Path Skew:      -0.019ns (0.627 - 0.646)
  Source Clock:         clock_ts<2> rising at 0.000ns
  Destination Clock:    clock_ts<2> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/enable__[2].enable_/out_enable to ts/error[2].error/binary_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y20.YQ      Tcko                  0.580   ts/enable__[2].enable_/out_enable
                                                       ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.G3      net (fanout=72)       2.686   ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.Y       Tilo                  0.707   ts/error[2].error/binary_not0001
                                                       ts/error[2].error/binary_not00011
    SLICE_X25Y59.CE      net (fanout=12)       2.377   ts/error[2].error/binary_not0001
    SLICE_X25Y59.CLK     Tceck                 0.311   ts/error[2].error/binary<22>
                                                       ts/error[2].error/binary_23
    -------------------------------------------------  ---------------------------
    Total                                      6.661ns (1.598ns logic, 5.063ns route)
                                                       (24.0% logic, 76.0% route)

--------------------------------------------------------------------------------
Slack:                  8.520ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/enable__[2].enable_/out_enable (FF)
  Destination:          ts/error[2].error/binary_22 (FF)
  Requirement:          15.200ns
  Data Path Delay:      6.661ns (Levels of Logic = 1)
  Clock Path Skew:      -0.019ns (0.627 - 0.646)
  Source Clock:         clock_ts<2> rising at 0.000ns
  Destination Clock:    clock_ts<2> rising at 15.200ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/enable__[2].enable_/out_enable to ts/error[2].error/binary_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y20.YQ      Tcko                  0.580   ts/enable__[2].enable_/out_enable
                                                       ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.G3      net (fanout=72)       2.686   ts/enable__[2].enable_/out_enable
    SLICE_X28Y42.Y       Tilo                  0.707   ts/error[2].error/binary_not0001
                                                       ts/error[2].error/binary_not00011
    SLICE_X25Y59.CE      net (fanout=12)       2.377   ts/error[2].error/binary_not0001
    SLICE_X25Y59.CLK     Tceck                 0.311   ts/error[2].error/binary<22>
                                                       ts/error[2].error/binary_22
    -------------------------------------------------  ---------------------------
    Total                                      6.661ns (1.598ns logic, 5.063ns route)
                                                       (24.0% logic, 76.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ts_clock_3 = PERIOD TIMEGRP "ts_clock_3" 24.4 ns HIGH 
50%;

 1203 paths analyzed, 555 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.643ns.
--------------------------------------------------------------------------------
Slack:                  17.757ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[3].packet/a_count_l (FF)
  Destination:          ts/packet[3].packet/out_data_23 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.659ns (Levels of Logic = 3)
  Clock Path Skew:      0.016ns (0.499 - 0.483)
  Source Clock:         clock_ts<3> rising at 0.000ns
  Destination Clock:    clock_ts<3> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[3].packet/a_count_l to ts/packet[3].packet/out_data_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y21.YQ      Tcko                  0.676   ts/packet[3].packet/b_count_l
                                                       ts/packet[3].packet/a_count_l
    SLICE_X6Y10.G3       net (fanout=7)        1.515   ts/packet[3].packet/a_count_l
    SLICE_X6Y10.Y        Tilo                  0.707   ts/packet[3].packet/N9
                                                       ts/packet[3].packet/out_data_mux0000<10>11
    SLICE_X6Y10.F4       net (fanout=3)        0.136   ts/packet[3].packet/N1
    SLICE_X6Y10.X        Tilo                  0.692   ts/packet[3].packet/N9
                                                       ts/packet[3].packet/out_data_mux0000<10>21
    SLICE_X2Y1.G2        net (fanout=19)       2.116   ts/packet[3].packet/N9
    SLICE_X2Y1.CLK       Tgck                  0.817   ts/packet[3].packet/out_data<23>
                                                       ts/packet[3].packet/out_data_mux0000<8>1
                                                       ts/packet[3].packet/out_data_23
    -------------------------------------------------  ---------------------------
    Total                                      6.659ns (2.892ns logic, 3.767ns route)
                                                       (43.4% logic, 56.6% route)

--------------------------------------------------------------------------------
Slack:                  17.792ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[3].packet/a_count_h (FF)
  Destination:          ts/packet[3].packet/out_data_23 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.603ns (Levels of Logic = 3)
  Clock Path Skew:      -0.005ns (0.637 - 0.642)
  Source Clock:         clock_ts<3> rising at 0.000ns
  Destination Clock:    clock_ts<3> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[3].packet/a_count_h to ts/packet[3].packet/out_data_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y17.XQ      Tcko                  0.631   ts/packet[3].packet/a_count_h
                                                       ts/packet[3].packet/a_count_h
    SLICE_X6Y10.G1       net (fanout=7)        1.504   ts/packet[3].packet/a_count_h
    SLICE_X6Y10.Y        Tilo                  0.707   ts/packet[3].packet/N9
                                                       ts/packet[3].packet/out_data_mux0000<10>11
    SLICE_X6Y10.F4       net (fanout=3)        0.136   ts/packet[3].packet/N1
    SLICE_X6Y10.X        Tilo                  0.692   ts/packet[3].packet/N9
                                                       ts/packet[3].packet/out_data_mux0000<10>21
    SLICE_X2Y1.G2        net (fanout=19)       2.116   ts/packet[3].packet/N9
    SLICE_X2Y1.CLK       Tgck                  0.817   ts/packet[3].packet/out_data<23>
                                                       ts/packet[3].packet/out_data_mux0000<8>1
                                                       ts/packet[3].packet/out_data_23
    -------------------------------------------------  ---------------------------
    Total                                      6.603ns (2.847ns logic, 3.756ns route)
                                                       (43.1% logic, 56.9% route)

--------------------------------------------------------------------------------
Slack:                  17.796ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ts/packet[3].packet/count_h_0 (FF)
  Destination:          ts/packet[3].packet/count_h_5 (FF)
  Requirement:          24.400ns
  Data Path Delay:      6.552ns (Levels of Logic = 3)
  Clock Path Skew:      -0.052ns (0.206 - 0.258)
  Source Clock:         clock_ts<3> rising at 0.000ns
  Destination Clock:    clock_ts<3> rising at 24.400ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ts/packet[3].packet/count_h_0 to ts/packet[3].packet/count_h_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y23.YQ      Tcko                  0.676   ts/packet[3].packet/count_h<0>
                                                       ts/packet[3].packet/count_h_0
    SLICE_X24Y20.G3      net (fanout=7)        1.661   ts/packet[3].packet/count_h<0>
    SLICE_X24Y20.Y       Tilo                  0.707   ts/packet[3].packet/count_h_not000112
                                                       ts/packet[3].packet/count_h_mux0000<1>11
    SLICE_X24Y20.F4      net (fanout=3)        0.173   ts/packet[3].packet/N7
    SLICE_X24Y20.X       Tilo                  0.692   ts/packet[3].packet/count_h_not000112
                                                       ts/packet[3].packet/count_h_not000112
    SLICE_X22Y20.F1      net (fanout=1)        0.463   ts/packet[3].packet/count_h_not000112
    SLICE_X22Y20.X       Tilo                  0.692   ts/packet[3].packet/count_h_not0001
                                                       ts/packet[3].packet/count_h_not000139
    SLICE_X23Y21.CE      net (fanout=5)        1.177   ts/packet[3].packet/count_h_not0001
    SLICE_X23Y21.CLK     Tceck                 0.311   ts/packet[3].packet/count_h<5>
                                                       ts/packet[3].packet/count_h_5
    -------------------------------------------------  ---------------------------
    Total                                      6.552ns (3.078ns logic, 3.474ns route)
                                                       (47.0% logic, 53.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP 
"clock_pci_ram_clock" TS_pci_clock / 3         HIGH 50%;

 6853 paths analyzed, 980 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   9.846ns.
--------------------------------------------------------------------------------
Slack:                  0.154ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ram/ram/page_count_3 (FF)
  Destination:          ram/ram/page_address_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.734ns (Levels of Logic = 4)
  Clock Path Skew:      -0.112ns (0.450 - 0.562)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ram/ram/page_count_3 to ram/ram/page_address_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y28.YQ      Tcko                  0.580   ram/ram/page_count<2>
                                                       ram/ram/page_count_3
    SLICE_X16Y29.F2      net (fanout=3)        1.373   ram/ram/page_count<3>
    SLICE_X16Y29.X       Tilo                  0.692   ram/ram/read_begin21
                                                       ram/ram/read_begin21
    SLICE_X16Y30.G1      net (fanout=1)        0.449   ram/ram/read_begin21
    SLICE_X16Y30.Y       Tilo                  0.707   ram/ram/read_begin
                                                       ram/ram/read_begin46_SW0
    SLICE_X16Y30.F4      net (fanout=1)        0.060   ram/ram/read_begin46_SW0/O
    SLICE_X16Y30.X       Tilo                  0.692   ram/ram/read_begin
                                                       ram/ram/read_begin46
    SLICE_X27Y19.F4      net (fanout=8)        1.620   ram/ram/read_begin
    SLICE_X27Y19.X       Tilo                  0.643   ram/ram/page_address_not0001
                                                       ram/ram/page_address_not00011
    SLICE_X28Y8.CE       net (fanout=9)        2.607   ram/ram/page_address_not0001
    SLICE_X28Y8.CLK      Tceck                 0.311   ram/ram/page_address<3>
                                                       ram/ram/page_address_2
    -------------------------------------------------  ---------------------------
    Total                                      9.734ns (3.625ns logic, 6.109ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------
Slack:                  0.154ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ram/ram/page_count_3 (FF)
  Destination:          ram/ram/page_address_3 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.734ns (Levels of Logic = 4)
  Clock Path Skew:      -0.112ns (0.450 - 0.562)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ram/ram/page_count_3 to ram/ram/page_address_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y28.YQ      Tcko                  0.580   ram/ram/page_count<2>
                                                       ram/ram/page_count_3
    SLICE_X16Y29.F2      net (fanout=3)        1.373   ram/ram/page_count<3>
    SLICE_X16Y29.X       Tilo                  0.692   ram/ram/read_begin21
                                                       ram/ram/read_begin21
    SLICE_X16Y30.G1      net (fanout=1)        0.449   ram/ram/read_begin21
    SLICE_X16Y30.Y       Tilo                  0.707   ram/ram/read_begin
                                                       ram/ram/read_begin46_SW0
    SLICE_X16Y30.F4      net (fanout=1)        0.060   ram/ram/read_begin46_SW0/O
    SLICE_X16Y30.X       Tilo                  0.692   ram/ram/read_begin
                                                       ram/ram/read_begin46
    SLICE_X27Y19.F4      net (fanout=8)        1.620   ram/ram/read_begin
    SLICE_X27Y19.X       Tilo                  0.643   ram/ram/page_address_not0001
                                                       ram/ram/page_address_not00011
    SLICE_X28Y8.CE       net (fanout=9)        2.607   ram/ram/page_address_not0001
    SLICE_X28Y8.CLK      Tceck                 0.311   ram/ram/page_address<3>
                                                       ram/ram/page_address_3
    -------------------------------------------------  ---------------------------
    Total                                      9.734ns (3.625ns logic, 6.109ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------
Slack:                  0.182ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/count/out_write_count_0 (FF)
  Destination:          ram/ram/page_address_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.721ns (Levels of Logic = 5)
  Clock Path Skew:      -0.097ns (0.588 - 0.685)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/count/out_write_count_0 to ram/ram/page_address_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y40.XQ      Tcko                  0.591   fifo/fifo/count/out_write_count<0>
                                                       fifo/fifo/count/out_write_count_0
    SLICE_X15Y41.F1      net (fanout=1)        0.501   fifo/fifo/count/out_write_count<0>
    SLICE_X15Y41.COUT    Topcyf                1.195   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_lut<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X15Y42.CIN     net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X15Y42.COUT    Tbyp                  0.130   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<2>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X15Y43.CIN     net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X15Y43.XB      Tcinxb                0.296   ram/ram/read_begin_cmp_le0000
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
    SLICE_X16Y30.F1      net (fanout=1)        1.135   ram/ram/read_begin_cmp_le0000
    SLICE_X16Y30.X       Tilo                  0.692   ram/ram/read_begin
                                                       ram/ram/read_begin46
    SLICE_X27Y19.F4      net (fanout=8)        1.620   ram/ram/read_begin
    SLICE_X27Y19.X       Tilo                  0.643   ram/ram/page_address_not0001
                                                       ram/ram/page_address_not00011
    SLICE_X28Y8.CE       net (fanout=9)        2.607   ram/ram/page_address_not0001
    SLICE_X28Y8.CLK      Tceck                 0.311   ram/ram/page_address<3>
                                                       ram/ram/page_address_2
    -------------------------------------------------  ---------------------------
    Total                                      9.721ns (3.858ns logic, 5.863ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP 
"in_pci_clock";

 1076 paths analyzed, 255 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   5.961ns.
--------------------------------------------------------------------------------
Slack:                  0.039ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_trdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_26 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.299ns (Levels of Logic = 6)
  Clock Path Delay:     2.338ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G3.I                 Tiopi                 1.256   io_pci_trdy
                                                       io_pci_trdy
                                                       io_pci_trdy_IOBUF/IBUF
                                                       io_pci_trdy.DELAY_ADJ
                                                       ProtoComp96.ISELMUX.3
    SLICE_X6Y42.G3       net (fanout=21)       0.852   N204
    SLICE_X6Y42.Y        Tilo                  0.707   fifo/_COND_65<2>
                                                       pci/pci/initiator/out_local_done_mux0000112
    SLICE_X8Y39.F4       net (fanout=21)       0.723   pci/pci/initiator/N12
    SLICE_X8Y39.X        Tilo                  0.692   fifo/read_index_0_2
                                                       fifo/_COND_65<1>1
    SLICE_X12Y43.F2      net (fanout=32)       1.502   fifo/_COND_65<1>
    SLICE_X12Y43.X       Tilo                  0.692   fifo_read_data<26>
                                                       fifo/Mram_read_data27.SLICEM_F
    SLICE_X13Y42.G3      net (fanout=1)        0.075   fifo_read_data<26>
    SLICE_X13Y42.Y       Tilo                  0.648   pci/pci/ad_cbe/out_pci_ad<26>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001961
    SLICE_X13Y42.F2      net (fanout=1)        0.430   pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001961/O
    SLICE_X13Y42.CLK     Tfck                  0.722   pci/pci/ad_cbe/out_pci_ad<26>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001987
                                                       pci/pci/ad_cbe/out_pci_ad_26
    -------------------------------------------------  ---------------------------
    Total                                      8.299ns (4.717ns logic, 3.582ns route)
                                                       (56.8% logic, 43.2% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X13Y42.CLK     net (fanout=713)      0.877   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.338ns (1.285ns logic, 1.053ns route)
                                                       (55.0% logic, 45.0% route)

--------------------------------------------------------------------------------
Slack:                  0.053ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_trdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_19 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.261ns (Levels of Logic = 6)
  Clock Path Delay:     2.314ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_19
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G3.I                 Tiopi                 1.256   io_pci_trdy
                                                       io_pci_trdy
                                                       io_pci_trdy_IOBUF/IBUF
                                                       io_pci_trdy.DELAY_ADJ
                                                       ProtoComp96.ISELMUX.3
    SLICE_X6Y42.G3       net (fanout=21)       0.852   N204
    SLICE_X6Y42.Y        Tilo                  0.707   fifo/_COND_65<2>
                                                       pci/pci/initiator/out_local_done_mux0000112
    SLICE_X11Y39.F4      net (fanout=21)       0.705   pci/pci/initiator/N12
    SLICE_X11Y39.X       Tilo                  0.643   fifo/read_index_1_2
                                                       fifo/_COND_65<0>1
    SLICE_X14Y44.F1      net (fanout=32)       1.560   fifo/_COND_65<0>
    SLICE_X14Y44.X       Tilo                  0.692   fifo_read_data<19>
                                                       fifo/Mram_read_data20.SLICEM_F
    SLICE_X15Y45.G4      net (fanout=1)        0.046   fifo_read_data<19>
    SLICE_X15Y45.Y       Tilo                  0.648   pci/pci/ad_cbe/out_pci_ad<19>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux000011106
    SLICE_X15Y45.F2      net (fanout=1)        0.430   pci/pci/ad_cbe/Mmux_out_pci_ad_mux000011106/O
    SLICE_X15Y45.CLK     Tfck                  0.722   pci/pci/ad_cbe/out_pci_ad<19>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux000011132
                                                       pci/pci/ad_cbe/out_pci_ad_19
    -------------------------------------------------  ---------------------------
    Total                                      8.261ns (4.668ns logic, 3.593ns route)
                                                       (56.5% logic, 43.5% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_19
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X15Y45.CLK     net (fanout=713)      0.853   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.314ns (1.285ns logic, 1.029ns route)
                                                       (55.5% logic, 44.5% route)

--------------------------------------------------------------------------------
Slack:                  0.086ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_irdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_15 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.331ns (Levels of Logic = 5)
  Clock Path Delay:     2.417ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_irdy to pci/pci/ad_cbe/out_pci_ad_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    J1.I                 Tiopi                 1.256   io_pci_irdy
                                                       io_pci_irdy
                                                       io_pci_irdy_IOBUF/IBUF
                                                       io_pci_irdy.DELAY_ADJ
                                                       ProtoComp96.ISELMUX.2
    SLICE_X4Y45.G4       net (fanout=6)        1.402   N203
    SLICE_X4Y45.Y        Tilo                  0.707   pci/pci/initiator/ad/out_pci_a_enable62
                                                       pci/pci/initiator/ad/out_pci_a_enable62_SW0
    SLICE_X4Y45.F3       net (fanout=1)        0.043   N571
    SLICE_X4Y45.X        Tilo                  0.692   pci/pci/initiator/ad/out_pci_a_enable62
                                                       pci/pci/initiator/ad/out_pci_a_enable62
    SLICE_X4Y41.G2       net (fanout=4)        0.680   pci/pci/initiator/ad/out_pci_a_enable62
    SLICE_X4Y41.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/initiator/ad/out_pci_a_enable83_1
    SLICE_X11Y34.F1      net (fanout=17)       2.122   pci/pci/initiator/ad/out_pci_a_enable83
    SLICE_X11Y34.CLK     Tfck                  0.722   pci/pci/ad_cbe/out_pci_ad<15>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00007139
                                                       pci/pci/ad_cbe/out_pci_ad_15
    -------------------------------------------------  ---------------------------
    Total                                      8.331ns (4.084ns logic, 4.247ns route)
                                                       (49.0% logic, 51.0% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X11Y34.CLK     net (fanout=713)      0.956   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.417ns (1.285ns logic, 1.132ns route)
                                                       (53.2% logic, 46.8% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE 
COMP "in_pci_clock";

 321 paths analyzed, 95 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   8.085ns.
--------------------------------------------------------------------------------
Slack:                  0.915ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_15 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.502ns (Levels of Logic = 6)
  Clock Path Delay:     2.417ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X3Y42.G2       net (fanout=8)        1.420   in_pci_gnt_IBUF
    SLICE_X3Y42.Y        Tilo                  0.648   N538
                                                       pci/pci/initiator/continue1
    SLICE_X2Y42.F1       net (fanout=7)        0.853   pci/pci/initiator/continue
    SLICE_X2Y42.X        Tilo                  0.692   N536
                                                       pci/pci/initiator/ad/out_pci_a_enable13_SW0_G
    SLICE_X4Y38.G3       net (fanout=1)        0.714   N536
    SLICE_X4Y38.X        Tif5x                 0.987   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41_F
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.G3       net (fanout=4)        0.381   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/initiator/ad/out_pci_a_enable83_1
    SLICE_X11Y34.F1      net (fanout=17)       2.122   pci/pci/initiator/ad/out_pci_a_enable83
    SLICE_X11Y34.CLK     Tfck                  0.722   pci/pci/ad_cbe/out_pci_ad<15>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00007139
                                                       pci/pci/ad_cbe/out_pci_ad_15
    -------------------------------------------------  ---------------------------
    Total                                     10.502ns (5.012ns logic, 5.490ns route)
                                                       (47.7% logic, 52.3% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X11Y34.CLK     net (fanout=713)      0.956   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.417ns (1.285ns logic, 1.132ns route)
                                                       (53.2% logic, 46.8% route)

--------------------------------------------------------------------------------
Slack:                  0.972ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_3 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.434ns (Levels of Logic = 6)
  Clock Path Delay:     2.406ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X3Y42.G2       net (fanout=8)        1.420   in_pci_gnt_IBUF
    SLICE_X3Y42.Y        Tilo                  0.648   N538
                                                       pci/pci/initiator/continue1
    SLICE_X2Y42.F1       net (fanout=7)        0.853   pci/pci/initiator/continue
    SLICE_X2Y42.X        Tilo                  0.692   N536
                                                       pci/pci/initiator/ad/out_pci_a_enable13_SW0_G
    SLICE_X4Y38.G3       net (fanout=1)        0.714   N536
    SLICE_X4Y38.X        Tif5x                 0.987   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41_F
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.G3       net (fanout=4)        0.381   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/initiator/ad/out_pci_a_enable83_1
    SLICE_X11Y36.F1      net (fanout=17)       2.054   pci/pci/initiator/ad/out_pci_a_enable83
    SLICE_X11Y36.CLK     Tfck                  0.722   pci/pci/ad_cbe/out_pci_ad<3>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00002683
                                                       pci/pci/ad_cbe/out_pci_ad_3
    -------------------------------------------------  ---------------------------
    Total                                     10.434ns (5.012ns logic, 5.422ns route)
                                                       (48.0% logic, 52.0% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X11Y36.CLK     net (fanout=713)      0.945   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.406ns (1.285ns logic, 1.121ns route)
                                                       (53.4% logic, 46.6% route)

--------------------------------------------------------------------------------
Slack:                  1.005ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_31 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.401ns (Levels of Logic = 6)
  Clock Path Delay:     2.406ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_31
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X3Y42.G2       net (fanout=8)        1.420   in_pci_gnt_IBUF
    SLICE_X3Y42.Y        Tilo                  0.648   N538
                                                       pci/pci/initiator/continue1
    SLICE_X2Y42.F1       net (fanout=7)        0.853   pci/pci/initiator/continue
    SLICE_X2Y42.X        Tilo                  0.692   N536
                                                       pci/pci/initiator/ad/out_pci_a_enable13_SW0_G
    SLICE_X4Y38.G3       net (fanout=1)        0.714   N536
    SLICE_X4Y38.X        Tif5x                 0.987   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41_F
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.G3       net (fanout=4)        0.381   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X4Y41.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/initiator/ad/out_pci_a_enable83_1
    SLICE_X10Y37.F4      net (fanout=17)       1.941   pci/pci/initiator/ad/out_pci_a_enable83
    SLICE_X10Y37.CLK     Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<31>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00002583
                                                       pci/pci/ad_cbe/out_pci_ad_31
    -------------------------------------------------  ---------------------------
    Total                                     10.401ns (5.092ns logic, 5.309ns route)
                                                       (49.0% logic, 51.0% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_31
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.176   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X10Y37.CLK     net (fanout=713)      0.945   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.406ns (1.285ns logic, 1.121ns route)
                                                       (53.4% logic, 46.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP 
"in_pci_clock";

 84 paths analyzed, 42 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   9.569ns.
--------------------------------------------------------------------------------
Slack:                  0.431ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_enable (FF)
  Destination:          io_pci_ad<8> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.813ns (Levels of Logic = 1)
  Clock Path Delay:     2.756ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.220   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X4Y41.CLK      net (fanout=713)      1.059   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.756ns (1.477ns logic, 1.279ns route)
                                                       (53.6% logic, 46.4% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.XQ       Tcko                  0.631   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/ad_cbe/out_pci_ad_enable
    N1.T1                net (fanout=33)       3.166   pci/pci/ad_cbe/out_pci_ad_enable
    N1.PAD               Tiotp                 3.016   io_pci_ad<8>
                                                       io_pci_ad_8_IOBUF/OBUFT
                                                       io_pci_ad<8>
    -------------------------------------------------  ---------------------------
    Total                                      6.813ns (3.647ns logic, 3.166ns route)
                                                       (53.5% logic, 46.5% route)

--------------------------------------------------------------------------------
Slack:                  0.688ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_enable (FF)
  Destination:          io_pci_ad<6> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.556ns (Levels of Logic = 1)
  Clock Path Delay:     2.756ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.220   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X4Y41.CLK      net (fanout=713)      1.059   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.756ns (1.477ns logic, 1.279ns route)
                                                       (53.6% logic, 46.4% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<6>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.XQ       Tcko                  0.631   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/ad_cbe/out_pci_ad_enable
    L4.T1                net (fanout=33)       2.909   pci/pci/ad_cbe/out_pci_ad_enable
    L4.PAD               Tiotp                 3.016   io_pci_ad<6>
                                                       io_pci_ad_6_IOBUF/OBUFT
                                                       io_pci_ad<6>
    -------------------------------------------------  ---------------------------
    Total                                      6.556ns (3.647ns logic, 2.909ns route)
                                                       (55.6% logic, 44.4% route)

--------------------------------------------------------------------------------
Slack:                  0.700ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_enable (FF)
  Destination:          io_pci_ad<5> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.544ns (Levels of Logic = 1)
  Clock Path Delay:     2.756ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.220   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X4Y41.CLK      net (fanout=713)      1.059   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.756ns (1.477ns logic, 1.279ns route)
                                                       (53.6% logic, 46.4% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.XQ       Tcko                  0.631   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/ad_cbe/out_pci_ad_enable
    P1.T1                net (fanout=33)       2.897   pci/pci/ad_cbe/out_pci_ad_enable
    P1.PAD               Tiotp                 3.016   io_pci_ad<5>
                                                       io_pci_ad_5_IOBUF/OBUFT
                                                       io_pci_ad<5>
    -------------------------------------------------  ---------------------------
    Total                                      6.544ns (3.647ns logic, 2.897ns route)
                                                       (55.7% logic, 44.3% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP 
"in_pci_clock";

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   8.374ns.
--------------------------------------------------------------------------------
Slack:                  2.626ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/initiator/enable (FF)
  Destination:          out_pci_req (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          11.000ns
  Data Path Delay:      5.682ns (Levels of Logic = 1)
  Clock Path Delay:     2.692ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/initiator/enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R7.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y1.I0      net (fanout=4)        0.220   clock_pci1
    BUFGMUX_X2Y1.O       Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X8Y52.CLK      net (fanout=713)      0.995   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.692ns (1.477ns logic, 1.215ns route)
                                                       (54.9% logic, 45.1% route)

  Maximum Data Path: pci/pci/initiator/enable to out_pci_req
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y52.XQ       Tcko                  0.631   pci/pci/initiator/enable
                                                       pci/pci/initiator/enable
    A4.O1                net (fanout=20)       1.810   pci/pci/initiator/enable
    A4.PAD               Tioop                 3.241   out_pci_req
                                                       out_pci_req_OBUFT
                                                       out_pci_req
    -------------------------------------------------  ---------------------------
    Total                                      5.682ns (3.872ns logic, 1.810ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "ts_in_0" OFFSET = IN 6.2 ns VALID 5 ns BEFORE COMP 
"in_ts_clock<0>";

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   4.974ns.
--------------------------------------------------------------------------------
Slack:                  1.226ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_byte<0> (PAD)
  Destination:          ts/io[0].io/ts_byte_0 (FF)
  Destination Clock:    clock_ts<0> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.269ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_byte<0> to ts/io[0].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B12.ICLK1            Tiopickd              7.243   in_ts_byte<0>
                                                       in_ts_byte<0>
                                                       in_ts_byte_0_IBUF
                                                       in_ts_byte<0>.DELAY_ADJ
                                                       ts/io[0].io/ts_byte_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 1.214   in_ts_clock<0>
                                                       in_ts_clock<0>
                                                       clock/ts/bit[0].ibufg
                                                       in_ts_clock<0>.DELAY_ADJ
    BUFGMUX_X1Y10.I0     net (fanout=1)        0.027   clock_ts<0>1
    BUFGMUX_X1Y10.O      Tgi0o                 0.199   clock_ts<0>_BUFG
                                                       clock_ts<0>_BUFG
    B12.ICLK1            net (fanout=103)      0.829   clock_ts<0>
    -------------------------------------------------  ---------------------------
    Total                                      2.269ns (1.413ns logic, 0.856ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------
Slack:                  1.226ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_valid<0> (PAD)
  Destination:          ts/io[0].io/ts_valid_0 (FF)
  Destination Clock:    clock_ts<0> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.269ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_valid<0> to ts/io[0].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A12.ICLK1            Tiopickd              7.243   in_ts_valid<0>
                                                       in_ts_valid<0>
                                                       in_ts_valid_0_IBUF
                                                       in_ts_valid<0>.DELAY_ADJ
                                                       ts/io[0].io/ts_valid_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 1.214   in_ts_clock<0>
                                                       in_ts_clock<0>
                                                       clock/ts/bit[0].ibufg
                                                       in_ts_clock<0>.DELAY_ADJ
    BUFGMUX_X1Y10.I0     net (fanout=1)        0.027   clock_ts<0>1
    BUFGMUX_X1Y10.O      Tgi0o                 0.199   clock_ts<0>_BUFG
                                                       clock_ts<0>_BUFG
    A12.ICLK1            net (fanout=103)      0.829   clock_ts<0>
    -------------------------------------------------  ---------------------------
    Total                                      2.269ns (1.413ns logic, 0.856ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------
Slack:                  1.231ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_data<0> (PAD)
  Destination:          ts/io[0].io/ts_data_0 (FF)
  Destination Clock:    clock_ts<0> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.274ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_data<0> to ts/io[0].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A13.ICLK1            Tiopickd              7.243   in_ts_data<0>
                                                       in_ts_data<0>
                                                       in_ts_data_0_IBUF
                                                       in_ts_data<0>.DELAY_ADJ
                                                       ts/io[0].io/ts_data_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<0> to ts/io[0].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 1.214   in_ts_clock<0>
                                                       in_ts_clock<0>
                                                       clock/ts/bit[0].ibufg
                                                       in_ts_clock<0>.DELAY_ADJ
    BUFGMUX_X1Y10.I0     net (fanout=1)        0.027   clock_ts<0>1
    BUFGMUX_X1Y10.O      Tgi0o                 0.199   clock_ts<0>_BUFG
                                                       clock_ts<0>_BUFG
    A13.ICLK1            net (fanout=103)      0.834   clock_ts<0>
    -------------------------------------------------  ---------------------------
    Total                                      2.274ns (1.413ns logic, 0.861ns route)
                                                       (62.1% logic, 37.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "ts_in_1" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP 
"in_ts_clock<1>";

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.082ns.
--------------------------------------------------------------------------------
Slack:                  2.918ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_error<1> (PAD)
  Destination:          ts/io[1].io/ts_error_0 (FF)
  Destination Clock:    clock_ts<1> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.261ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_error<1> to ts/io[1].io/ts_error_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A6.ICLK1             Tiopick               2.343   in_ts_error<1>
                                                       in_ts_error<1>
                                                       in_ts_error_1_IBUF
                                                       in_ts_error<1>.DELAY_ADJ
                                                       ts/io[1].io/ts_error_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_error_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_ts_clock<1>
                                                       in_ts_clock<1>
                                                       clock/ts/bit[1].ibufg
                                                       in_ts_clock<1>.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=1)        0.027   clock_ts<1>1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_ts<1>_BUFG
                                                       clock_ts<1>_BUFG
    A6.ICLK1             net (fanout=104)      0.821   clock_ts<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.261ns (1.413ns logic, 0.848ns route)
                                                       (62.5% logic, 37.5% route)

--------------------------------------------------------------------------------
Slack:                  2.936ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_data<1> (PAD)
  Destination:          ts/io[1].io/ts_data_0 (FF)
  Destination Clock:    clock_ts<1> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.279ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_data<1> to ts/io[1].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B10.ICLK1            Tiopick               2.343   in_ts_data<1>
                                                       in_ts_data<1>
                                                       in_ts_data_1_IBUF
                                                       in_ts_data<1>.DELAY_ADJ
                                                       ts/io[1].io/ts_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_ts_clock<1>
                                                       in_ts_clock<1>
                                                       clock/ts/bit[1].ibufg
                                                       in_ts_clock<1>.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=1)        0.027   clock_ts<1>1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_ts<1>_BUFG
                                                       clock_ts<1>_BUFG
    B10.ICLK1            net (fanout=104)      0.839   clock_ts<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.279ns (1.413ns logic, 0.866ns route)
                                                       (62.0% logic, 38.0% route)

--------------------------------------------------------------------------------
Slack:                  2.938ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_byte<1> (PAD)
  Destination:          ts/io[1].io/ts_byte_0 (FF)
  Destination Clock:    clock_ts<1> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.281ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_byte<1> to ts/io[1].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A7.ICLK1             Tiopick               2.343   in_ts_byte<1>
                                                       in_ts_byte<1>
                                                       in_ts_byte_1_IBUF
                                                       in_ts_byte<1>.DELAY_ADJ
                                                       ts/io[1].io/ts_byte_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<1> to ts/io[1].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_ts_clock<1>
                                                       in_ts_clock<1>
                                                       clock/ts/bit[1].ibufg
                                                       in_ts_clock<1>.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=1)        0.027   clock_ts<1>1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_ts<1>_BUFG
                                                       clock_ts<1>_BUFG
    A7.ICLK1             net (fanout=104)      0.841   clock_ts<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.281ns (1.413ns logic, 0.868ns route)
                                                       (61.9% logic, 38.1% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "ts_in_2" OFFSET = IN 6.2 ns VALID 5 ns BEFORE COMP 
"in_ts_clock<2>";

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   4.965ns.
--------------------------------------------------------------------------------
Slack:                  1.235ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_byte<2> (PAD)
  Destination:          ts/io[2].io/ts_byte_0 (FF)
  Destination Clock:    clock_ts<2> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.278ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_byte<2> to ts/io[2].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D11.ICLK1            Tiopickd              7.243   in_ts_byte<2>
                                                       in_ts_byte<2>
                                                       in_ts_byte_2_IBUF
                                                       in_ts_byte<2>.DELAY_ADJ
                                                       ts/io[2].io/ts_byte_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.214   in_ts_clock<2>
                                                       in_ts_clock<2>
                                                       clock/ts/bit[2].ibufg
                                                       in_ts_clock<2>.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.027   clock_ts<2>1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_ts<2>_BUFG
                                                       clock_ts<2>_BUFG
    D11.ICLK1            net (fanout=104)      0.838   clock_ts<2>
    -------------------------------------------------  ---------------------------
    Total                                      2.278ns (1.413ns logic, 0.865ns route)
                                                       (62.0% logic, 38.0% route)

--------------------------------------------------------------------------------
Slack:                  1.235ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_data<2> (PAD)
  Destination:          ts/io[2].io/ts_data_0 (FF)
  Destination Clock:    clock_ts<2> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.278ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_data<2> to ts/io[2].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C12.ICLK1            Tiopickd              7.243   in_ts_data<2>
                                                       in_ts_data<2>
                                                       in_ts_data_2_IBUF
                                                       in_ts_data<2>.DELAY_ADJ
                                                       ts/io[2].io/ts_data_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.214   in_ts_clock<2>
                                                       in_ts_clock<2>
                                                       clock/ts/bit[2].ibufg
                                                       in_ts_clock<2>.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.027   clock_ts<2>1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_ts<2>_BUFG
                                                       clock_ts<2>_BUFG
    C12.ICLK1            net (fanout=104)      0.838   clock_ts<2>
    -------------------------------------------------  ---------------------------
    Total                                      2.278ns (1.413ns logic, 0.865ns route)
                                                       (62.0% logic, 38.0% route)

--------------------------------------------------------------------------------
Slack:                  1.236ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_valid<2> (PAD)
  Destination:          ts/io[2].io/ts_valid_0 (FF)
  Destination Clock:    clock_ts<2> rising at 0.000ns
  Requirement:          6.200ns
  Data Path Delay:      7.243ns (Levels of Logic = 0)
  Clock Path Delay:     2.279ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_valid<2> to ts/io[2].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C11.ICLK1            Tiopickd              7.243   in_ts_valid<2>
                                                       in_ts_valid<2>
                                                       in_ts_valid_2_IBUF
                                                       in_ts_valid<2>.DELAY_ADJ
                                                       ts/io[2].io/ts_valid_0
    -------------------------------------------------  ---------------------------
    Total                                      7.243ns (7.243ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<2> to ts/io[2].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.214   in_ts_clock<2>
                                                       in_ts_clock<2>
                                                       clock/ts/bit[2].ibufg
                                                       in_ts_clock<2>.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.027   clock_ts<2>1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_ts<2>_BUFG
                                                       clock_ts<2>_BUFG
    C11.ICLK1            net (fanout=104)      0.839   clock_ts<2>
    -------------------------------------------------  ---------------------------
    Total                                      2.279ns (1.413ns logic, 0.866ns route)
                                                       (62.0% logic, 38.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "ts_in_3" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP 
"in_ts_clock<3>";

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.074ns.
--------------------------------------------------------------------------------
Slack:                  2.926ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_valid<3> (PAD)
  Destination:          ts/io[3].io/ts_valid_0 (FF)
  Destination Clock:    clock_ts<3> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.269ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_valid<3> to ts/io[3].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D10.ICLK1            Tiopick               2.343   in_ts_valid<3>
                                                       in_ts_valid<3>
                                                       in_ts_valid_3_IBUF
                                                       in_ts_valid<3>.DELAY_ADJ
                                                       ts/io[3].io/ts_valid_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_valid_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D9.I                 Tiopi                 1.214   in_ts_clock<3>
                                                       in_ts_clock<3>
                                                       clock/ts/bit[3].ibufg
                                                       in_ts_clock<3>.DELAY_ADJ
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.027   clock_ts<3>1
    BUFGMUX_X2Y11.O      Tgi0o                 0.199   clock_ts<3>_BUFG
                                                       clock_ts<3>_BUFG
    D10.ICLK1            net (fanout=104)      0.829   clock_ts<3>
    -------------------------------------------------  ---------------------------
    Total                                      2.269ns (1.413ns logic, 0.856ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------
Slack:                  2.938ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_data<3> (PAD)
  Destination:          ts/io[3].io/ts_data_0 (FF)
  Destination Clock:    clock_ts<3> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.281ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_data<3> to ts/io[3].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C10.ICLK1            Tiopick               2.343   in_ts_data<3>
                                                       in_ts_data<3>
                                                       in_ts_data_3_IBUF
                                                       in_ts_data<3>.DELAY_ADJ
                                                       ts/io[3].io/ts_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D9.I                 Tiopi                 1.214   in_ts_clock<3>
                                                       in_ts_clock<3>
                                                       clock/ts/bit[3].ibufg
                                                       in_ts_clock<3>.DELAY_ADJ
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.027   clock_ts<3>1
    BUFGMUX_X2Y11.O      Tgi0o                 0.199   clock_ts<3>_BUFG
                                                       clock_ts<3>_BUFG
    C10.ICLK1            net (fanout=104)      0.841   clock_ts<3>
    -------------------------------------------------  ---------------------------
    Total                                      2.281ns (1.413ns logic, 0.868ns route)
                                                       (61.9% logic, 38.1% route)

--------------------------------------------------------------------------------
Slack:                  2.949ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_ts_byte<3> (PAD)
  Destination:          ts/io[3].io/ts_byte_0 (FF)
  Destination Clock:    clock_ts<3> rising at 0.000ns
  Requirement:          3.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.292ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_ts_byte<3> to ts/io[3].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D14.ICLK1            Tiopick               2.343   in_ts_byte<3>
                                                       in_ts_byte<3>
                                                       in_ts_byte_3_IBUF
                                                       in_ts_byte<3>.DELAY_ADJ
                                                       ts/io[3].io/ts_byte_0
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_ts_clock<3> to ts/io[3].io/ts_byte_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D9.I                 Tiopi                 1.214   in_ts_clock<3>
                                                       in_ts_clock<3>
                                                       clock/ts/bit[3].ibufg
                                                       in_ts_clock<3>.DELAY_ADJ
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.027   clock_ts<3>1
    BUFGMUX_X2Y11.O      Tgi0o                 0.199   clock_ts<3>_BUFG
                                                       clock_ts<3>_BUFG
    D14.ICLK1            net (fanout=104)      0.852   clock_ts<3>
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (1.413ns logic, 0.879ns route)
                                                       (61.6% logic, 38.4% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_pci_clock
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_pci_clock                   |     30.000ns|     16.608ns|     29.538ns|            0|            0|        21466|         6853|
| TS_clock_pci_ram_clock        |     10.000ns|      9.846ns|          N/A|            0|            0|         6853|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock in_pci_clock
-------------+------------+------------+------------------+--------+
             |  Setup to  |  Hold to   |                  | Clock  |
Source       | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
-------------+------------+------------+------------------+--------+
in_pci_gnt   |    8.085(R)|   -1.511(R)|clock_pci         |   0.000|
in_pci_idsel |    4.699(R)|   -1.287(R)|clock_pci         |   0.000|
io_pci_ad<0> |    4.766(R)|   -1.366(R)|clock_pci         |   0.000|
io_pci_ad<1> |    4.769(R)|   -1.370(R)|clock_pci         |   0.000|
io_pci_ad<2> |    4.766(R)|   -1.366(R)|clock_pci         |   0.000|
io_pci_ad<3> |    4.769(R)|   -1.370(R)|clock_pci         |   0.000|
io_pci_ad<4> |    4.802(R)|   -1.409(R)|clock_pci         |   0.000|
io_pci_ad<5> |    4.776(R)|   -1.377(R)|clock_pci         |   0.000|
io_pci_ad<6> |    4.802(R)|   -1.409(R)|clock_pci         |   0.000|
io_pci_ad<7> |    4.776(R)|   -1.377(R)|clock_pci         |   0.000|
io_pci_ad<8> |    4.795(R)|   -1.400(R)|clock_pci         |   0.000|
io_pci_ad<9> |    4.791(R)|   -1.396(R)|clock_pci         |   0.000|
io_pci_ad<10>|    4.795(R)|   -1.400(R)|clock_pci         |   0.000|
io_pci_ad<11>|    4.768(R)|   -1.368(R)|clock_pci         |   0.000|
io_pci_ad<12>|    4.771(R)|   -1.372(R)|clock_pci         |   0.000|
io_pci_ad<13>|    4.783(R)|   -1.386(R)|clock_pci         |   0.000|
io_pci_ad<14>|    4.771(R)|   -1.372(R)|clock_pci         |   0.000|
io_pci_ad<15>|    4.789(R)|   -1.394(R)|clock_pci         |   0.000|
io_pci_ad<16>|    4.813(R)|   -1.422(R)|clock_pci         |   0.000|
io_pci_ad<17>|    4.809(R)|   -1.417(R)|clock_pci         |   0.000|
io_pci_ad<18>|    4.743(R)|   -1.339(R)|clock_pci         |   0.000|
io_pci_ad<19>|    4.753(R)|   -1.351(R)|clock_pci         |   0.000|
io_pci_ad<20>|    4.791(R)|   -1.395(R)|clock_pci         |   0.000|
io_pci_ad<21>|    4.791(R)|   -1.395(R)|clock_pci         |   0.000|
io_pci_ad<22>|    4.743(R)|   -1.339(R)|clock_pci         |   0.000|
io_pci_ad<23>|    4.753(R)|   -1.351(R)|clock_pci         |   0.000|
io_pci_ad<24>|    4.821(R)|   -1.431(R)|clock_pci         |   0.000|
io_pci_ad<25>|    4.736(R)|   -1.331(R)|clock_pci         |   0.000|
io_pci_ad<26>|    4.744(R)|   -1.340(R)|clock_pci         |   0.000|
io_pci_ad<27>|    4.696(R)|   -1.284(R)|clock_pci         |   0.000|
io_pci_ad<28>|    4.826(R)|   -1.437(R)|clock_pci         |   0.000|
io_pci_ad<29>|    4.696(R)|   -1.284(R)|clock_pci         |   0.000|
io_pci_ad<30>|    4.826(R)|   -1.437(R)|clock_pci         |   0.000|
io_pci_ad<31>|    4.813(R)|   -1.421(R)|clock_pci         |   0.000|
io_pci_cbe<0>|    4.791(R)|   -1.396(R)|clock_pci         |   0.000|
io_pci_cbe<1>|    4.768(R)|   -1.368(R)|clock_pci         |   0.000|
io_pci_cbe<2>|    4.792(R)|   -1.397(R)|clock_pci         |   0.000|
io_pci_cbe<3>|    4.885(R)|   -1.331(R)|clock_pci         |   0.000|
io_pci_devsel|    5.909(R)|   -0.643(R)|clock_pci         |   0.000|
io_pci_frame |    5.898(R)|   -0.231(R)|clock_pci         |   0.000|
io_pci_irdy  |    5.914(R)|   -0.608(R)|clock_pci         |   0.000|
io_pci_stop  |    5.822(R)|   -0.383(R)|clock_pci         |   0.000|
io_pci_trdy  |    5.961(R)|   -0.420(R)|clock_pci         |   0.000|
-------------+------------+------------+------------------+--------+

Setup/Hold to clock in_ts_clock<0>
--------------+------------+------------+------------------+--------+
              |  Setup to  |  Hold to   |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
in_ts_byte<0> |    4.974(R)|   -1.624(R)|clock_ts<0>       |   0.000|
in_ts_data<0> |    4.969(R)|   -1.618(R)|clock_ts<0>       |   0.000|
in_ts_error<0>|    4.969(R)|   -1.618(R)|clock_ts<0>       |   0.000|
in_ts_valid<0>|    4.974(R)|   -1.624(R)|clock_ts<0>       |   0.000|
--------------+------------+------------+------------------+--------+

Setup/Hold to clock in_ts_clock<1>
--------------+------------+------------+------------------+--------+
              |  Setup to  |  Hold to   |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
in_ts_byte<1> |    0.062(R)|    1.435(R)|clock_ts<1>       |   0.000|
in_ts_data<1> |    0.064(R)|    1.432(R)|clock_ts<1>       |   0.000|
in_ts_error<1>|    0.082(R)|    1.411(R)|clock_ts<1>       |   0.000|
in_ts_valid<1>|    0.058(R)|    1.440(R)|clock_ts<1>       |   0.000|
--------------+------------+------------+------------------+--------+

Setup/Hold to clock in_ts_clock<2>
--------------+------------+------------+------------------+--------+
              |  Setup to  |  Hold to   |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
in_ts_byte<2> |    4.965(R)|   -1.613(R)|clock_ts<2>       |   0.000|
in_ts_data<2> |    4.965(R)|   -1.613(R)|clock_ts<2>       |   0.000|
in_ts_error<2>|    4.956(R)|   -1.602(R)|clock_ts<2>       |   0.000|
in_ts_valid<2>|    4.964(R)|   -1.612(R)|clock_ts<2>       |   0.000|
--------------+------------+------------+------------------+--------+

Setup/Hold to clock in_ts_clock<3>
--------------+------------+------------+------------------+--------+
              |  Setup to  |  Hold to   |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
in_ts_byte<3> |    0.051(R)|    1.447(R)|clock_ts<3>       |   0.000|
in_ts_data<3> |    0.062(R)|    1.435(R)|clock_ts<3>       |   0.000|
in_ts_error<3>|    0.051(R)|    1.447(R)|clock_ts<3>       |   0.000|
in_ts_valid<3>|    0.074(R)|    1.420(R)|clock_ts<3>       |   0.000|
--------------+------------+------------+------------------+--------+

Clock in_pci_clock to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  | Clock  |
Destination  |   to PAD   |Internal Clock(s) | Phase  |
-------------+------------+------------------+--------+
io_pci_ad<0> |    8.859(R)|clock_pci         |   0.000|
io_pci_ad<1> |    8.726(R)|clock_pci         |   0.000|
io_pci_ad<2> |    8.852(R)|clock_pci         |   0.000|
io_pci_ad<3> |    9.027(R)|clock_pci         |   0.000|
io_pci_ad<4> |    8.612(R)|clock_pci         |   0.000|
io_pci_ad<5> |    9.300(R)|clock_pci         |   0.000|
io_pci_ad<6> |    9.312(R)|clock_pci         |   0.000|
io_pci_ad<7> |    9.092(R)|clock_pci         |   0.000|
io_pci_ad<8> |    9.569(R)|clock_pci         |   0.000|
io_pci_ad<9> |    8.505(R)|clock_pci         |   0.000|
io_pci_ad<10>|    9.268(R)|clock_pci         |   0.000|
io_pci_ad<11>|    8.760(R)|clock_pci         |   0.000|
io_pci_ad<12>|    8.529(R)|clock_pci         |   0.000|
io_pci_ad<13>|    8.568(R)|clock_pci         |   0.000|
io_pci_ad<14>|    8.760(R)|clock_pci         |   0.000|
io_pci_ad<15>|    8.801(R)|clock_pci         |   0.000|
io_pci_ad<16>|    8.562(R)|clock_pci         |   0.000|
io_pci_ad<17>|    8.507(R)|clock_pci         |   0.000|
io_pci_ad<18>|    8.719(R)|clock_pci         |   0.000|
io_pci_ad<19>|    8.553(R)|clock_pci         |   0.000|
io_pci_ad<20>|    8.562(R)|clock_pci         |   0.000|
io_pci_ad<21>|    8.517(R)|clock_pci         |   0.000|
io_pci_ad<22>|    8.570(R)|clock_pci         |   0.000|
io_pci_ad<23>|    8.771(R)|clock_pci         |   0.000|
io_pci_ad<24>|    8.334(R)|clock_pci         |   0.000|
io_pci_ad<25>|    8.770(R)|clock_pci         |   0.000|
io_pci_ad<26>|    8.655(R)|clock_pci         |   0.000|
io_pci_ad<27>|    8.496(R)|clock_pci         |   0.000|
io_pci_ad<28>|    8.781(R)|clock_pci         |   0.000|
io_pci_ad<29>|    8.148(R)|clock_pci         |   0.000|
io_pci_ad<30>|    8.620(R)|clock_pci         |   0.000|
io_pci_ad<31>|    9.063(R)|clock_pci         |   0.000|
io_pci_cbe<0>|    8.623(R)|clock_pci         |   0.000|
io_pci_cbe<1>|    7.937(R)|clock_pci         |   0.000|
io_pci_cbe<2>|    7.564(R)|clock_pci         |   0.000|
io_pci_cbe<3>|    8.010(R)|clock_pci         |   0.000|
io_pci_devsel|    8.160(R)|clock_pci         |   0.000|
io_pci_frame |    8.022(R)|clock_pci         |   0.000|
io_pci_irdy  |    8.324(R)|clock_pci         |   0.000|
io_pci_stop  |    8.031(R)|clock_pci         |   0.000|
io_pci_trdy  |    8.413(R)|clock_pci         |   0.000|
out_pci_par  |    7.079(R)|clock_pci         |   0.000|
out_pci_req  |    8.374(R)|clock_pci         |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock in_pci_clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_pci_clock   |   16.608|         |    2.335|         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_ts_clock<0>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<0> |    6.481|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_ts_clock<1>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<1> |    6.721|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_ts_clock<2>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<2> |    6.680|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_ts_clock<3>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_ts_clock<3> |    6.643|         |         |         |
---------------+---------+---------+---------+---------+

TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 5.730; Ideal Clock Offset To Actual Clock -0.004; 
-------------+------------+------------+---------+---------+-------------+
             |            |            |  Setup  |  Hold   |Source Offset|
Source       |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------+------------+------------+---------+---------+-------------+
in_pci_idsel |    4.699(R)|   -1.287(R)|    1.301|    1.087|        0.107|
io_pci_ad<0> |    4.766(R)|   -1.366(R)|    1.234|    1.166|        0.034|
io_pci_ad<1> |    4.769(R)|   -1.370(R)|    1.231|    1.170|        0.031|
io_pci_ad<2> |    4.766(R)|   -1.366(R)|    1.234|    1.166|        0.034|
io_pci_ad<3> |    4.769(R)|   -1.370(R)|    1.231|    1.170|        0.031|
io_pci_ad<4> |    4.802(R)|   -1.409(R)|    1.198|    1.209|       -0.006|
io_pci_ad<5> |    4.776(R)|   -1.377(R)|    1.224|    1.177|        0.023|
io_pci_ad<6> |    4.802(R)|   -1.409(R)|    1.198|    1.209|       -0.006|
io_pci_ad<7> |    4.776(R)|   -1.377(R)|    1.224|    1.177|        0.023|
io_pci_ad<8> |    4.795(R)|   -1.400(R)|    1.205|    1.200|        0.003|
io_pci_ad<9> |    4.791(R)|   -1.396(R)|    1.209|    1.196|        0.007|
io_pci_ad<10>|    4.795(R)|   -1.400(R)|    1.205|    1.200|        0.003|
io_pci_ad<11>|    4.768(R)|   -1.368(R)|    1.232|    1.168|        0.032|
io_pci_ad<12>|    4.771(R)|   -1.372(R)|    1.229|    1.172|        0.029|
io_pci_ad<13>|    4.783(R)|   -1.386(R)|    1.217|    1.186|        0.016|
io_pci_ad<14>|    4.771(R)|   -1.372(R)|    1.229|    1.172|        0.029|
io_pci_ad<15>|    4.789(R)|   -1.394(R)|    1.211|    1.194|        0.009|
io_pci_ad<16>|    4.813(R)|   -1.422(R)|    1.187|    1.222|       -0.017|
io_pci_ad<17>|    4.809(R)|   -1.417(R)|    1.191|    1.217|       -0.013|
io_pci_ad<18>|    4.743(R)|   -1.339(R)|    1.257|    1.139|        0.059|
io_pci_ad<19>|    4.753(R)|   -1.351(R)|    1.247|    1.151|        0.048|
io_pci_ad<20>|    4.791(R)|   -1.395(R)|    1.209|    1.195|        0.007|
io_pci_ad<21>|    4.791(R)|   -1.395(R)|    1.209|    1.195|        0.007|
io_pci_ad<22>|    4.743(R)|   -1.339(R)|    1.257|    1.139|        0.059|
io_pci_ad<23>|    4.753(R)|   -1.351(R)|    1.247|    1.151|        0.048|
io_pci_ad<24>|    4.821(R)|   -1.431(R)|    1.179|    1.231|       -0.026|
io_pci_ad<25>|    4.736(R)|   -1.331(R)|    1.264|    1.131|        0.067|
io_pci_ad<26>|    4.744(R)|   -1.340(R)|    1.256|    1.140|        0.058|
io_pci_ad<27>|    4.696(R)|   -1.284(R)|    1.304|    1.084|        0.110|
io_pci_ad<28>|    4.826(R)|   -1.437(R)|    1.174|    1.237|       -0.032|
io_pci_ad<29>|    4.696(R)|   -1.284(R)|    1.304|    1.084|        0.110|
io_pci_ad<30>|    4.826(R)|   -1.437(R)|    1.174|    1.237|       -0.032|
io_pci_ad<31>|    4.813(R)|   -1.421(R)|    1.187|    1.221|       -0.017|
io_pci_cbe<0>|    4.791(R)|   -1.396(R)|    1.209|    1.196|        0.007|
io_pci_cbe<1>|    4.768(R)|   -1.368(R)|    1.232|    1.168|        0.032|
io_pci_cbe<2>|    4.792(R)|   -1.397(R)|    1.208|    1.197|        0.005|
io_pci_cbe<3>|    4.885(R)|   -1.331(R)|    1.115|    1.131|       -0.008|
io_pci_devsel|    5.909(R)|   -0.643(R)|    0.091|    0.443|       -0.176|
io_pci_frame |    5.898(R)|   -0.231(R)|    0.102|    0.031|        0.035|
io_pci_irdy  |    5.914(R)|   -0.608(R)|    0.086|    0.408|       -0.161|
io_pci_stop  |    5.822(R)|   -0.383(R)|    0.178|    0.183|       -0.003|
io_pci_trdy  |    5.961(R)|   -0.420(R)|    0.039|    0.220|       -0.091|
-------------+------------+------------+---------+---------+-------------+
Worst Case   |            |            |         |         |             |
Summary      |       5.961|      -0.231|    0.039|    0.031|             |
-------------+------------+------------+---------+---------+-------------+

TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 6.574; Ideal Clock Offset To Actual Clock 0.198; 
------------+------------+------------+---------+---------+-------------+
            |            |            |  Setup  |  Hold   |Source Offset|
Source      |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
------------+------------+------------+---------+---------+-------------+
in_pci_gnt  |    8.085(R)|   -1.511(R)|    0.915|    1.311|       -0.198|
------------+------------+------------+---------+---------+-------------+
Worst Case  |            |            |         |         |             |
Summary     |       8.085|      -1.511|    0.915|    1.311|             |
------------+------------+------------+---------+---------+-------------+

TIMEGRP "ts_in_0" OFFSET = IN 6.2 ns VALID 5 ns BEFORE COMP "in_ts_clock<0>";
Worst Case Data Window 3.356; Ideal Clock Offset To Actual Clock -0.404; 
--------------+------------+------------+---------+---------+-------------+
              |            |            |  Setup  |  Hold   |Source Offset|
Source        |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<0> |    4.974(R)|   -1.624(R)|    1.226|    0.424|        0.401|
in_ts_data<0> |    4.969(R)|   -1.618(R)|    1.231|    0.418|        0.407|
in_ts_error<0>|    4.969(R)|   -1.618(R)|    1.231|    0.418|        0.407|
in_ts_valid<0>|    4.974(R)|   -1.624(R)|    1.226|    0.424|        0.401|
--------------+------------+------------+---------+---------+-------------+
Worst Case    |            |            |         |         |             |
Summary       |       4.974|      -1.618|    1.226|    0.418|             |
--------------+------------+------------+---------+---------+-------------+

TIMEGRP "ts_in_1" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "in_ts_clock<1>";
Worst Case Data Window 1.522; Ideal Clock Offset To Actual Clock -0.679; 
--------------+------------+------------+---------+---------+-------------+
              |            |            |  Setup  |  Hold   |Source Offset|
Source        |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<1> |    0.062(R)|    1.435(R)|    2.938|    1.565|        0.687|
in_ts_data<1> |    0.064(R)|    1.432(R)|    2.936|    1.568|        0.684|
in_ts_error<1>|    0.082(R)|    1.411(R)|    2.918|    1.589|        0.665|
in_ts_valid<1>|    0.058(R)|    1.440(R)|    2.942|    1.560|        0.691|
--------------+------------+------------+---------+---------+-------------+
Worst Case    |            |            |         |         |             |
Summary       |       0.082|       1.440|    2.918|    1.560|             |
--------------+------------+------------+---------+---------+-------------+

TIMEGRP "ts_in_2" OFFSET = IN 6.2 ns VALID 5 ns BEFORE COMP "in_ts_clock<2>";
Worst Case Data Window 3.363; Ideal Clock Offset To Actual Clock -0.417; 
--------------+------------+------------+---------+---------+-------------+
              |            |            |  Setup  |  Hold   |Source Offset|
Source        |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<2> |    4.965(R)|   -1.613(R)|    1.235|    0.413|        0.411|
in_ts_data<2> |    4.965(R)|   -1.613(R)|    1.235|    0.413|        0.411|
in_ts_error<2>|    4.956(R)|   -1.602(R)|    1.244|    0.402|        0.421|
in_ts_valid<2>|    4.964(R)|   -1.612(R)|    1.236|    0.412|        0.412|
--------------+------------+------------+---------+---------+-------------+
Worst Case    |            |            |         |         |             |
Summary       |       4.965|      -1.602|    1.235|    0.402|             |
--------------+------------+------------+---------+---------+-------------+

TIMEGRP "ts_in_3" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "in_ts_clock<3>";
Worst Case Data Window 1.521; Ideal Clock Offset To Actual Clock -0.687; 
--------------+------------+------------+---------+---------+-------------+
              |            |            |  Setup  |  Hold   |Source Offset|
Source        |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
--------------+------------+------------+---------+---------+-------------+
in_ts_byte<3> |    0.051(R)|    1.447(R)|    2.949|    1.553|        0.698|
in_ts_data<3> |    0.062(R)|    1.435(R)|    2.938|    1.565|        0.687|
in_ts_error<3>|    0.051(R)|    1.447(R)|    2.949|    1.553|        0.698|
in_ts_valid<3>|    0.074(R)|    1.420(R)|    2.926|    1.580|        0.673|
--------------+------------+------------+---------+---------+-------------+
Worst Case    |            |            |         |         |             |
Summary       |       0.074|       1.447|    2.926|    1.553|             |
--------------+------------+------------+---------+---------+-------------+

TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP "in_pci_clock";
Bus Skew: 2.490 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
io_pci_ad<0>                                   |        8.859|        1.780|
io_pci_ad<1>                                   |        8.726|        1.647|
io_pci_ad<2>                                   |        8.852|        1.773|
io_pci_ad<3>                                   |        9.027|        1.948|
io_pci_ad<4>                                   |        8.612|        1.533|
io_pci_ad<5>                                   |        9.300|        2.221|
io_pci_ad<6>                                   |        9.312|        2.233|
io_pci_ad<7>                                   |        9.092|        2.013|
io_pci_ad<8>                                   |        9.569|        2.490|
io_pci_ad<9>                                   |        8.505|        1.426|
io_pci_ad<10>                                  |        9.268|        2.189|
io_pci_ad<11>                                  |        8.760|        1.681|
io_pci_ad<12>                                  |        8.529|        1.450|
io_pci_ad<13>                                  |        8.568|        1.489|
io_pci_ad<14>                                  |        8.760|        1.681|
io_pci_ad<15>                                  |        8.801|        1.722|
io_pci_ad<16>                                  |        8.562|        1.483|
io_pci_ad<17>                                  |        8.507|        1.428|
io_pci_ad<18>                                  |        8.719|        1.640|
io_pci_ad<19>                                  |        8.553|        1.474|
io_pci_ad<20>                                  |        8.562|        1.483|
io_pci_ad<21>                                  |        8.517|        1.438|
io_pci_ad<22>                                  |        8.570|        1.491|
io_pci_ad<23>                                  |        8.771|        1.692|
io_pci_ad<24>                                  |        8.334|        1.255|
io_pci_ad<25>                                  |        8.770|        1.691|
io_pci_ad<26>                                  |        8.655|        1.576|
io_pci_ad<27>                                  |        8.496|        1.417|
io_pci_ad<28>                                  |        8.781|        1.702|
io_pci_ad<29>                                  |        8.148|        1.069|
io_pci_ad<30>                                  |        8.620|        1.541|
io_pci_ad<31>                                  |        9.063|        1.984|
io_pci_cbe<0>                                  |        8.623|        1.544|
io_pci_cbe<1>                                  |        7.937|        0.858|
io_pci_cbe<2>                                  |        7.564|        0.485|
io_pci_cbe<3>                                  |        8.010|        0.931|
io_pci_devsel                                  |        8.160|        1.081|
io_pci_frame                                   |        8.022|        0.943|
io_pci_irdy                                    |        8.324|        1.245|
io_pci_stop                                    |        8.031|        0.952|
io_pci_trdy                                    |        8.413|        1.334|
out_pci_par                                    |        7.079|        0.000|
-----------------------------------------------+-------------+-------------+

TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP "in_pci_clock";
Bus Skew: 0.000 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
out_pci_req                                    |        8.374|        0.000|
-----------------------------------------------+-------------+-------------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 34630 paths, 0 nets, and 10675 connections

Design statistics:
   Minimum period:  16.608ns{1}   (Maximum frequency:  60.212MHz)
   Minimum input required time before clock:   8.085ns
   Minimum output required time after clock:   9.569ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed TUE 21 OCT 0:51:39 2008 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 150 MB